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2003

Arquitecturas Basadas en el Contenido

XIV Jornadas de Paralelismo

R. González, A. Cristal, D. Ortega, and M. Valero
Optimal Use of Registers in Aggressive Superscalar Processors

XIV Jornadas de Paralelismo

A. Cristal, J. F. Martínez, J. Llosa, and M. Valero
A Case for Resource-conscious Out-of-order Processors

Computer Architecture Letters

A. Cristal, J. F. Martínez, J. Llosa, and M. Valero
Tolerating branch predictor latency on SMT

5th International Symposium on High Performance Computing (ISHPC-V)

A. Falcón, O. J. Santana, A. Ramirez, and M. Valero
An Analysis of Dynamic Instruction Streams

XIV Jornadas de Paralelismo

O. J. Santana, M. Galluzzi, A. Ramirez, and M. Valero
Latency Tolerant Branch Predictors

2003 International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'03)

O. J. Santana, A. Ramirez, and M. Valero
Improving Memory Latency Aware Fetch Policies for SMT Processors

5th International Symposium on High Performance Computing (ISHPC-V)

F. Cazorla, E. Fernández, A. Ramirez, and M. Valero
CDE: A Compiler-driven, Dependence-Centric, Eager-executing Architecture for the Billion Transistors Era

Workshop on Complexity-Effective Design (WCED 2003)

C. Acosta, S. Vajapeyam, A. Ramirez, and M. Valero
Dealing with Billions of Transistors

XIV Jornadas de Paralelismo

C. Acosta, M. Galluzzi, S. Vajapeyam, A. Ramirez, and M. Valero

2002

Large Virtual ROBs by Processor Checkpointing

A. Cristal, M. Valero, A. González, and J. Llosa

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