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2011

A Comprehensive Study of Conflict Resolution Policies in Hardware Transactional Memory

6th ACM SIGPLAN Workshop on Transactional Computing (TRANSACT)

E. Akpinar, S. Tomić, A. Cristal, O. Unsal, and M. Valero
Circuit Design of a Dual-Versioning L1 Data Cache for Optimistic Concurrency

21st Great Lakes Symposium on Very Large Scale Integration (GLSVLSI'11)

A. Seyedi, A. Armejach, A. Cristal, O. Unsal, I. Hur, and M. Valero
Integrating Dataflow Abstractions into Transactional Memory

First Workshop on Systems for Future Multi-Core Architectures (SFMA'11)

V. Gajinov, M. Milovanovic, O. Unsal, A. Cristal, E. Ayguade, and M. Valero
RMS-TM: A Comprehensive Benchmark Suite for Transactional Memory Systems

International Conference on Performance Engineering (ICPE 2011)

G. Kestor, V. Karakostas, O. Unsal, A. Cristal, I. Hur, and M. Valero
From Plasma to BeeFarm: Design Experience of an FPGA-based Multicore Prototype

The 7th International Symposium on Applied Reconfigurable Computing (ARC 2011)

N. Sönmez, O. Arcas, G. Sayilar, A. Cristal, I. Hur, O. Unsal, S. Singh, and M. Valero
Circuit Design of a Dual-Versioning L1 Data Cache

Integration The VLSI Journal

A. Seyedi, A. Armejach, A. Cristal, O. Unsal, I. Hur, and M. Valero
TMbox: A Flexible and Reconfigurable 16-core Hybrid Transactional Memory System

The 19th Annual IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM 2011)

N. Sönmez, O. Arcas, O. Pflucker, A. Cristal, O. Unsal, I. Hur, S. Singh, and M. Valero
Assessing Accelerator-based HPC Reverse Time Migration

Transactions on Parallel and Distributed Systems, Special Issue on Accelerators

M. Araya-Polo, J. Cabezas, M. Hanzich, M. Pericas, E. Morancho, I. Gelado, M. Shafiq, F. Rubio, J M.. Cela, E. Ayguade, N. Navarro, and M. Valero
Hybrid High-Performance Low-Power and Ultra-Low Energy Reliable Caches

International Conference on Computing Frontiers (CF)

B. Maric, J. Abella, F. Cazorla, and M. Valero
Exploiting Intra-Task Slack Time of Load Operations for DVFS in Hard Real-Time Multi-core Systems

In Work in Progess (WiP), under the the 24nd Euromicro Conference on Real-Time Systems (ECRTS 2011)

E. Quinones, J. Abella, F. Cazorla, and M. Valero

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