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2008

On-Chip memories, the OS perspective

5th HiPEAC Industrial Workshop

C. Villavieja, I. Gelado, A. Ramirez, and N. Navarro
Analysis of Video Filtering on the Cell Processor

2008 IEEE International Symposium on Circuits and Systems (ISCAS'08)

A. Azevedo, C. Meenderinck, B. Juurlink, M. Álvarez, and A. Ramirez
Parallel Scalability of H.264

1st Workshop on Programmability Issues for Multi-Core Computers (MULTIPROG)

C. Meenderinck, A. Azevedo, M. Álvarez, B. Juurlink, and A. Ramirez
Memory Management on Chip-MultiProcessors with on-chip Memories

Workshop on the Interaction between Operating Systems and Computer Architecture (WIOSCA'08)

I. Gelado, A. Ramirez, N. Navarro, and C. Villavieja
Preliminary Analysis of the Cell BE Processor Limitations for Sequence Alignment Applications

Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS'08)

S. Isaza, F. Sánchez, G. N. Gaydadjiev, A. Ramirez, and M. Valero
Virtual Private Machines: Hardware/Software Interactions in the Multicore Era

K. J. Nesbit, M. Moreto, F. Cazorla, A. Ramirez, M. Valero, and J. E. Smith

2007

CellSim: A Cell Processor Simulation Infrastructure

2007 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-07)

F. Cabarcas, A. Rico, D. Ródenas, X. Martorell, A. Ramirez, and E. Ayguade
Enlarging Instruction Streams

IEEE Transactions on Computers

O. J. Santana, A. Ramirez, and M. Valero
On the Problem of Minimizing Workload Execution Time in SMT Processors

International Conference on Embedded Computer Systems: Architectures, Modelling, and Simulation (SAMOS VII)

F. Cazorla, P. Knijnenburg, R. Sakellariou, E. Fernández, A. Ramirez, and M. Valero
Online Prediction of Throughput for Different Cache Sizes

XVIII Jornadas de Paralelismo

M. Moreto, F. Cazorla, A. Ramirez, and M. Valero

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