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2004

A Low Complexity Fetch Architecture for High Performance Superscalar Processors

ACM Transactions on Architecture and Compiler Optimizations (TACO)

M. Valero, O. J. Santana, A. Ramirez, and J. Lluis Larriba-Pey

2003

Tolerating branch predictor latency on SMT

5th International Symposium on High Performance Computing (ISHPC-V)

A. Falcón, O. J. Santana, A. Ramirez, and M. Valero
An Analysis of Dynamic Instruction Streams

XIV Jornadas de Paralelismo

O. J. Santana, M. Galluzzi, A. Ramirez, and M. Valero
Latency Tolerant Branch Predictors

2003 International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'03)

O. J. Santana, A. Ramirez, and M. Valero

2002

A Comprehensive Analysis of Indirect Branch Prediction

4th International Symposium on High Performance Computing (ISHPC-4)

O. J. Santana, A. Falcón, E. Fernández, P. Medina, A. Ramirez, and M. Valero
Studying New Ways for Improving Adaptive History Length Branch Predictors

4th International Symposium on High Performance Computing (ISHPC-4)

A. Falcón, O. J. Santana, P. Medina, E. Fernández, A. Ramirez, and M. Valero
Fetching Instruction Streams

35th Annual International Symposium on Microarchitecture (MICRO-35)

A. Ramirez, O. J. Santana, J. Lluis Larriba-Pey, and M. Valero

2001

An In-Depth Evaluation of the Multi-Stage Cascaded Predictor

XII Jornadas de Paralelismo, Valencia (Spain)

O. J. Santana, A. Falcón, E. Fernández, P. Medina, A. Ramirez, and M. Valero
An Analysis of Dynamic History Length Fitting

XII Jornadas de Paralelismo, Valencia (Spain)

A. Falcón, O. J. Santana, P. Medina, E. Fernández, A. Ramirez, and M. Valero

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