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Circuit Design of a Dual-Versioning L1 Data Cache for Optimistic Concurrency

Authors: Seyedi, Azam / Armejach, Adrià / Cristal, Adrián / Unsal, Osman / Hur, Ibrahim / Valero, Mateo

Publication: 21st Great Lakes Symposium on Very Large Scale Integration (GLSVLSI'11)

Place Published: Lausanne, Swaziland

Barcelona Supercomputing Center - Centro Nacional de Supercomputación
Source URL (retrieved on 11 Abr 2021 - 21:56): https://www.bsc.es/es/research-and-development/publications/circuit-design-dual-versioning-l1-data-cache-optimistic