Eventos

Mostrando 1 - 8 de 8
  • 09 May 2024

    SORS/WomenInBSC: "Accelerating Sparse Matrix Computations on Tensor Cores"

    Ubicación: [ONSITE] Room Severo Ochoa, Capella, BSC.
    2024-05-09 10:30:00 2024-05-09 10:30:00 Europe/Madrid SORS/WomenInBSC: "Accelerating Sparse Matrix Computations on Tensor Cores" For details, click on the following event link: https://www.bsc.es/es/research-and-development/research-seminars/sorswomeninbsc-accelerating-sparse-matrix-computations-tensor-cores [ONSITE] Room Severo Ochoa, Capella, BSC.
  • 30 Apr 2024

    SORS: "Advancing the State of the Art of Directive-Based Programming for GPUs: Runtime and Compilation"

    Ubicación: [HYBRID] Room 2-1-17, BSC Repsol Building and onlive via Zoom.
    Registrarse 2024-04-30 12:00:00 2024-04-30 12:00:00 Europe/Madrid SORS: "Advancing the State of the Art of Directive-Based Programming for GPUs: Runtime and Compilation" For details, click on the following event link: https://www.bsc.es/es/research-and-development/research-seminars/sors-advancing-the-state-the-art-directive-based-programming-gpus-runtime-and-compilation [HYBRID] Room 2-1-17, BSC Repsol Building and onlive via Zoom.
  • 11 Apr 2024

    SORS: "Generative AI for Agile Hardware Development"

    Ubicación: [HYBRID] Sala d' Actes FiB, UPC and onlive via Zoom.
    Registrarse 2024-04-11 14:30:00 2024-04-11 14:30:00 Europe/Madrid SORS: "Generative AI for Agile Hardware Development" For details, click on the following event link: https://www.bsc.es/es/research-and-development/research-seminars/sors-generative-ai-agile-hardware-development [HYBRID] Sala d' Actes FiB, UPC and onlive via Zoom.
  • 10 Apr 2024

    SORS: "Turquoise - 12nm 32-core RISC-V chip with a coherent mesh fabric for datacenter applications"

    Ubicación: [HYBRID] C6 Building, Room E101, UPC Campus Nord and onlive via Zoom.
    Registrarse 2024-04-10 12:00:00 2024-04-10 12:00:00 Europe/Madrid SORS: "Turquoise - 12nm 32-core RISC-V chip with a coherent mesh fabric for datacenter applications" For details, click on the following event link: https://www.bsc.es/es/research-and-development/research-seminars/sors-turquoise-12nm-32-core-risc-v-chip-coherent-mesh-fabric-datacenter-applications [HYBRID] C6 Building, Room E101, UPC Campus Nord and onlive via Zoom.
  • 20 Mar 2024

    SORS/WomenInBSC: "Sparse linear solver for transistor-level circuit simulation"

    Formación
    Ubicación: [ONSITE] Severo Ochoa Room, Capella, BSC
    2024-03-20 12:15:00 2024-03-20 12:15:00 Europe/Madrid SORS/WomenInBSC: "Sparse linear solver for transistor-level circuit simulation" For details, click on the following event link: https://www.bsc.es/es/research-and-development/research-seminars/sorswomeninbsc-sparse-linear-solver-transistor-level-circuit-simulation [ONSITE] Severo Ochoa Room, Capella, BSC
  • 05 Mar 2024

    SORS: "Reinventing virtual memory for modern hardware"

    Formación
    Ubicación: [ONSITE] Severo Ochoa Room, Capella, BSC
    Registrarse 2024-03-05 11:00:00 2024-03-05 11:00:00 Europe/Madrid SORS: "Reinventing virtual memory for modern hardware" For details, click on the following event link: https://www.bsc.es/es/research-and-development/research-seminars/sors-reinventing-virtual-memory-modern-hardware [ONSITE] Severo Ochoa Room, Capella, BSC
  • 05 Dec 2023
    Registrarse 2023-12-05 12:00:00 2023-12-05 12:00:00 Europe/Madrid SORS/WomenInBSC: "A dynamic task scheduling method based on run-time information from the Miss Status Holding Register (MSHR) tables" For details, click on the following event link: https://www.bsc.es/es/research-and-development/research-seminars/sorswomeninbsc-dynamic-task-scheduling-method-based-run-time-information-the-miss-status-holding Sala P2 B at Til·lers Building and online via Zoom  
  • 24 Nov 2023

    SORS: "A Potpourri of Ideas and Results in DRAM, FPGA Infrastructures, and RISC-V Processors"

    Ubicación: Room 2-1-17, Main building at BSC and onlive via Zoom
    Registrarse 2023-11-24 11:00:00 2023-11-24 11:00:00 Europe/Madrid SORS: "A Potpourri of Ideas and Results in DRAM, FPGA Infrastructures, and RISC-V Processors" For details, click on the following event link: https://www.bsc.es/es/research-and-development/research-seminars/sors-potpourri-ideas-and-results-dram-fpga-infrastructures-and-risc-v-processors Room 2-1-17, Main building at BSC and onlive via Zoom