8.2 Revistas

  • “Semi-automatic validation of cycle-accurate simulation infrastructures: The case for gem5-x86”.Future Generation Computer Systems 112, 832-847.
    JM Cebrian, A Barredo, H Caminal, M Moretó, M Casas, M Valero
     

    On the maturity of parallel applications for asymmetric multi-core processors.J. Parallel Distributed Comput. 127: 105-115 (2019) Published May 2019
    K.Chronaki, M. Moretó, M. Casas, A. Rico, RM. Badia, E. Ayguadé, M. Valero

    Using Arm's scalable vector extension on stencil codes.The Journal of Supercomputing 76(3): 2039-2062 (2020)Published on 8 April 2019
    A. Armejach, H. Caminal, JM. Cebrian, R. Langarita, R. González-Alberquilla, C. Adeniyi-Jones, M. Valero, M. Casas, M. Moretó

    Efficiency analysis of modern vector architectures: vector ALU sizes, core counts and clock frequencies.The Journal of Supercomputing 76(3): 1960-1979 (2020)
    Published on 4 April 2019.A. Barredo, JM. Cebrian, M. Valero, M. Casas, M. Moretó.

    A Hardware Runtime for Task-Based Programming Models.IEEE Trans. Parallel Distrib. Syst. 30(9): 1932-1946 (2019)Published 26th March 2019.
    X. Tan, J. Bosch, C. Álvarez, D. Jiménez-González, E. Ayguadé, M. Valero

    Guest Editorial: Special Issue on Network and Parallel Computing for Emerging Architectures and Applications.Int. J. Parallel Program. 47(3): 343-344 (2019) Published 23rd March 2019. F.Zhang, J. Zhai, M. Snir, H. Jin, H. Kasahara, M. Valero.

    The international race towards Exascale in EuropeCCF Transactions on High Performance Computing Springer Singapore.F. Gagliardi, M. Moreto, M. Olivieri, M.Valero. 2019, pages 1-11.

    Vector Processing-Aware Advanced Clock-Gating Techniques for Low-Power Fused Multiply-Add IEEE Transactions on Very Large Scale Integration (VLSI) SystemI. Ratkovic , O. Palomar, M. Stanic, O. S.Ünsal, A. Cristal and M. Valero to be published

    La Inteligencia Artificial y los Nuevos Puestos de Trabajo Revista La Maleta.Numero 31, Septiembre-Octubre 2018, pp.49-53.

    Performance and energy effects on task-based parallelized applications The Journal of Supercomputing H. Caminal, D. Caballero, J. M. Cebrián, R. Ferrer, M. Casas, M. Moretó, X. Martorell and M. Valero Vol 74, issue 6, pp 2627-2637, June 2018.

    Advances in the Hierarchical Emergent Behaviors (HEB) Approach to Autonomous Vehicles. IEEE Intelligent Transportation Systems Magazine. D. Roca, R. Milito, M. Nemirowsky and M. Valero. To be published

    Vector Processing-Aware Advanced Clock-Gating Techniques for Low-Power Fused Multiply-Add. IEEE Trans. VLSI Syst. 26(4): 639-652 (2018) I. Ratkovic, O. Palomar, M. Stanic, O. Unsal, A. Cristal and M. Valero:

    Reducing Cache Coherence Traffic with a NUMA-Aware Runtime Approach. IEEE Transacton on Parallel and Distributed Processing. Vol. 26, Issue 5. Pp.1174-1187, May 2018. P. Caheny, Ll. Alvarez, S. Derradji, M. Valero, M. Moreto and M. Casas.

    A general guide to applying machine learning to computer architecture SUPERFRI. Pendiente de publicar en 2018.
    D. Nemirovsky, T. Arkose, N. Markovic, M. Nemirovsky, O. Unsal, A. Cristal y M. Valero.

  • Asynchronous and Exact Forward Recovery for Detected Errors in Iterative SolversIEEE Computer Society – IEEE Transaction on Parallel and Distributed Systems. Volume: PP. Issue: 99.
    M. Moreto, L.Jaulmes, E. Ayguadé, J. Labarta, M. Valero y M. Casas. Marzo 2018.

    Técnicas de planificación de tareas para Sistemas asimétricos de múltiples núcleos.IEEE Transacciones en Sistemas paralelos y distriuidos; Volume 28, Issue 7, pp: 2074-2087, Julio 2017;
    K. Chronaki, A. Rico, M. Casas, M. Moretó, R. M. Badia, E. Ayguadé, J. Labarta and M. Valero.

  • Un diseño vectorial escalar integrado en un "In-Order ARM Core ACM TACO".Transacciones en Arquitectura y Optimización del código. Volume 14 Issue 2, Mayo 2017
    M. Stanic, O. Palomar, T. Hayes, I. Ratkovic, A. Cristal, O. Unsakl and M. Valero
  • Un acercamiento integrado a la monitorización táctica y An Intengrated approach for tactical monitoring and un pronóstico de propagación de incendios forestales basados en datosDiario "Fire Safety".M.M Valero, O. Rios, C. Mata, E. Pastor and E. Planas.
  • Programación heterogenea/Híbrida con ompss y sus implicaciones de software/hardware.Programación Multicore y Sistemas de Computación Many-core;Volume 86, pp: 101, Febrero ,2017
    E. Ayguade, R.M. Badia, P. Bellens, J. Bueno, I. Tsalouchidou Teruel and M. Valero.
  • Determinismo en un nivel de Bibleoteca estándar en Aplicaciones basadas en TMDiario internacional de Programación paralela; Volume 45, Issue 1, pp:17-29, Febrero 2017
    V. Smiljković, O. Ünsal, A. Cristal and M. Valero.
  • La Visión Hipeac 2017 HIPEAC red de Excelencia. Pp:138; Enero, 2017
    M. Duranton, K. De Bosschere, C. Gamrat, J. Maebe, H. Munk and O. Zendra.
  • Conductas emergentes en El Internet de las cosas: El Sistema definitivo de ulta gran escala IEEE-Micro temas especiales en IoT, el Internet de las cosas; IEEE Micro Noviembre-Diciembre 2016; Tema 6; Volumen 36
    D. Roca, D. Nemirosvky, M. Nemirosvjy, R. Milito and M. Valero
  • Asignación de subprocesos  de múltipes núcleos y Multithreaded: un enfoque estadísticoIEEE-TC.Vol 65, Tema 1. Pp.256-269, Enero 2016 P. Radojkovic, P. Carpenter, M. Moreto, V. Cakarevic, J. Verdú, A. Pajuelo, F. J. Cazorla, M. Nemirovsky and M. Valero
  • PARSECSs: Evaluando el impacte del paralelismo de las tareas en hechos en el lugar de referencia de PARSEC . ACM Transacciones de Arquitectura y Optimización de códigos (TACO), vol. 12, num. 4. Presentado en la Conferencia Internacional de Arquitecturas embebidas y de alto rendimiento y Compiladores (HiPEAC), Prague, Czech Republic, Enero 2016 D. Chasapis, M. Casas, M. Moreto, R. Vidal, E. Ayguade, J. Labarta and M. Valero
  • New Benchmarking Methodology and Programming Model for Big Data Processing International Journal of Distributed Sensor Networks, vol. 2015, pp. 1-7, 2015 A. Kos, S. Tomažič, J. Salom, N. Trifunovic, M. Valero and V. Milutinovic
  • Reimagining Heterogeneous Computing: a Functional Instruction Set Architecture (F-ISA) Computing Model IEEE Micro Special Issue on Alternative Computing Designs and Technologies 35(5), Septiembre 2015 D. Nemirovsky, N. Markovic, O. Unsal, M. Valero and A. Cristal
  • PARSECSs: Evaluating the Impact of Task Parallelism in the PARSEC Benchmark Suite ACM Transactions on Architecture and Code Optimization (TACO). Volume 12 Issue 4, 60(2016) D. Chasapis, M. Casas, M. Moretó, R. Vidal, E. Ayguadé, J. Labarta and M. Valero
  • Sensible Energy Accounting with Abstract Metering for Multicore Systems ACM Transactions on Architecture and Code Optimization (TACO). Volume 12 Issue 4, Diciembre 2015 Q. Liu, M. Moreto, J. Abella, F. J. Cazorla, D. A. Jiménez and M. Valero
  • Picos: A Hardware Runtime Architecture Support for OmpSs Future Generation Computing Systems. Vol. 53, Dic. 2015, pp.130-139 F. Yazdanpanah, C. Alvárez, D. Jiménez-Colás, R. M. Badia and M. Valero
  • Kernel to user mode code transition aware hardware scheduler for Asymmetric Single-ISA Multi-Core processor IEEE Micro 35(4), Julio 2015 N. Markovic, D. Nemirovsky, O. Unsal, M. Valero and A. Cristal
  • On-the-fly adaptive routing for dragonfly interconnection networks Journal of Supercomputing. Vol.01/03/2015.71(3) pp. 1116-1142 M. García, E. Vallejo, J.R. Beivide, C. Camarero, M. Valero, G. Rodríguez and C. Minkerberg
  • Hybrid Cache Designs for Reliable Hybrid High and Ultra-Low Voltage Operation TODAES-2013-P-723.R1. ACM Transactions on Design Automation of Electronic Systems (TODAES). Vol.20 (1), pp. 10-25, Noviembre 1, 2014 Hybrid Cache Designs for Reliable Hybrid High and Ultra-Low Voltage Operation
  • Thread Lock Section-aware Scheduling on Asymmetric Single-ISA Multi-Core IEEE Computer Architecture Letters (CAL) Volumen 14, No 2, pp: 160-163, ISSN: 1556-6056, Julio-Diciembre 2015N. Markovic, D. Nemirovsky, O. Unsal, M. Valero and A. Cristal
  • TERAFLUX: Harnessing dataflow in next generation teradevices. Microprocessors and Microsystems Embedded Hardware Design 38(8): 976-990 (2014) R. Giorgi, R. M. Badia, F. Bodin, A. Cohen, P. Evripidou, P. Faraboschi, B. Fechner, G. R. Gao, A. Garbade, R. Gayatri, S. Girbal, D. Goodman, B. Khan, S. Koliai, J. Landwehr, N. Minh Lê, F. Li, M. Luján, A. Mendelson, L. Morin, N. Navarro, T. Patejko, A. Pop, P. Trancoso, T. Ungerer, I. Watson, S. Weis, S. Zuckerman and M. Valero
  • Runtime-Aware Architectures: A first Approach Journal on Supercomputing Frontiers and Innovations. First Issue. Vol. 1, n.1, pp 28-43 M. Valero, M. Moreto, M. Casas, E. Ayguade and J. Labarta
  • Using Dynamic Runtime Testing for Rapid Development of Architectural Simulators International Journal of Parallel Programming, vol. 42 (1), pp. 119-139, Feb 2014 S. Tomic, A. Cristal, O. Unsal, and M. Valero
  • Supercomputadores: Imprescindibles para al Ciencia y la Ingenieria Revista Campus Milenio. México D.F, Nov, 21, 2013 M. Valero
  • Analyzing the Efficiency of L1 Caches for Reliable Hybrid-Voltage Operation Using EDC Codes IEEE Transactions on Very Large Scale Integration Systems. Vol. 22, (10). PP. 2212-2215, Octubre, 1, 2014 B. Maric, J. Abella and M. Valero
  • Editorial. Revista Computación y Sistema Vol 18(4), 2014 M. Valero and U. Cortés
  • Per-task Energy Accounting in Computing Systems IEEE Computer Architecture Letters (CAL).Volume 13, num. 2, pp. 85-88, Julio 2014 Q. Liu, V. Jiménez, M. Moreto, J. Abella, F. J. Cazorla and M. Valero
  • Programmability and portability for exascale: Top down programming methodology and tools with StarSs In Journal of Computational Science, available online February, 11th. 2013 http://dx.doi.org/10.1016/j.jocs.2013.01.008, pp. 450-456 V. Subotić, S. Brinkmann, V. Marjanović, R. M. Badia, J. Gracia, C. Niethammer, E. Ayguade, J. Labarta and M. Valero
  • Moving from Petaflops to Petadata Communications of the ACM, Vol. 56, No. 5, pp. 39-42, Mayo 2013 M. Flynn, O. Mencer, V. Milutinovic, G. Rakocevic, P. Stenström, R. Trobec and M. Valero
  • Overview of Acceleration Results of Maxeler FPGA Machines IPSI Transactions on Internet Research, Julio 2013, Volume 5, Number 1, pp. 1-4 J. Salom, H. Fujii and M. Valero
  • SMT Malleability in IBM Power5 and IBM Power6 Processors IEEE Transactions on Computers. Vol. 62, (4), pp. 813-826, Abril 2013 A. Morari, C. Boneti, R. Giogiosa, F. J. Cazorla, Chenyong, A. Buyuktosunoglu , P. Bose and M. Valero
  • Programmability and Portability for Exascale: Top-Down Programming Methodology and Tools with StasSs Elsevier, Journal of Computational Science. Feb, 2013. www.sciencedirect.com/science/article/pii/S1877750313000203 V. Subotic, S. Brinkmann, V. Marjanovíc, R. M. Badía, J. Gracia, C. Niethammer, E. Ayguadé, J. Labarta and M. Valero
  • Fair CPU Accounting in CMP+SMT Processors TACO. Vol. 9, (4), Enero 2013, pp.50 C. Luque, M. Moreto, F. J. Cazorla, and M. Valero
  • Hardware Support for accurate per-task energy metering in multicore systems TACO, 10 (4), 50, 2013 Q. Liu, M. Moretó, V. Jiménez, J. Abella, J. F. Cazoral and M. Valero
  • Thread Assignment of Multithreaded Network Applications in Multicore/Multithreaded Processors IEEEE TPDS, Transactions on Parallel and Distributed Systems”.Vol. 24, no. 12, pp. 2513-2525, 2013 P. Radojkovic, V. Cakarevic, J. Verdú, A. Pajuelo, F. J. Cazorla, M. Nemirovsky and M. Valero
  • The Problem of Evaluating CPU+GPU Systems with 3D Visualization Appliacations IEEE Micro Jounal. Issue Nov/Dec, Vol. 32, Issue 6, pp. 17-27,año 2012 J. Verdú, A. Pajuelo and M. Valero
  • Resource-bounded multicore emulation using Beefarm Microprocessors and Microsystems - Embedded Hardware Design. Vol. 36, No. 8, pp. 620-631, Nov. 2012 O. Arcas, N. Sönmez, G. Sayilar, S. Singh, O. Unsal, A. Cristal, I. Hur and M. Valero
  • Circuit Design of a Dual-Versioning L1 Data Cache Integration Integration, the VLSI Journal. Vol. 45, No. 3, pp. 237-245. Junio 2012 A. Seyedi, A. Armejach, A. Cristal, O. Unsal, I. Hur and M. Valero
  • Dynamic Tolerance Region Computing for Multimedia IEEE Transactions on Computers. Vol. 61, No. 5, pp. 650-665, Mayo 2012 C. Alvárez, J. Corbal and M. Valero
  • On the simulation of large-scale architectures using multiple application abstraction levels TACO, Vol 8, No. 4, 36, Enero 2012 A. Rico, F. Cabarcas, C. Villavieja, M. Pavlovic, A. Vega, Y. Etsion, A. Ramírez and M. Valero.
  • Profiling and Optimizing Transactional Memory Applications International Journal of Parallel Programming (IJPP),Vol. 40, No. 1, pp. 25-56. Feb. 2012 F. Zyulkyarov, S. Stipic, T. Harris, O. Unsal, A. Cristal, I. Hur and M. Valero
  • Understanding the Future of Energy-Performance Trade-off Via DVFS in HPC Environment IEEE Journal of Parallel and Distributed Computing, IEEE-JPDC. Vol. 72, pp.579-590. Enero, 2012 M. Etinski, J. Corbalán, J. Labarta and M. Valero
  • CPU Accounting for Multicore Processors IEEE Transactions on Computers. Vol. 61, Number 2, pp. 251-264, 2012 C. Luque, M. Moreto, F. J. Cazorla, R. Gioiosa, A. Buyukttosunoglu and M. Valero.
  • Parallel job scheduling for power constrained HPC systems Parallel Computing. Vol. 38, No.12, pp. 615-630, Dic. 2012 M. Etinski, J. Corbalán, J. Labarta and M. Valero
  • Hardware transactional memory with software-defined conflicts TACO. Vol. 8, No. 4, Enero. 2012 J. R. Titos, M. E. Acacio, J. M. García, T. Harris, A. Cristal, O. Unsal, I. Hur and M. Valero
  • An overview of Selected Hybrid and Reconfigurable Architectures 2012 IEEE INTERNATIONAL CONFERENCE ON INDUSTRIAL TECHNOLOGY (ICIT), (2012), pp. 444-449 S. Stajanovic, D. Bojic, M. Bojovic, M. Valero, V. Milutinovic
  • A Survey of Dual Data Cache Systems 2012. IEEE INTERNATIONAL CONFERENCE ON INDUSTRIAL TECHNOLOGY (ICIT), (2012), pp. 450-456 Z. Sustran, S. Stojanovic, G. Rakocevic, V. Milutinovic, and M. Valero
  • Scalable Multicore Architectures for Long DNA Sequence Comparison Concurrency and Computation: Practice and Experience.Vol. 23, No. 17, pp. 2205-2219, 2011 F. Sánchez, F. Cabarcas, A. Ramírez and M. Valero
  • Energy-Aware Accounting and Billing in Large-Scale Computing Facilities IEEE Micro Jornal. Vol 31 (3), pp. 60-71, 2011 V. Jiménez, F. J. Cazorla, R. Gioiosa, E. Kursun, C. Isci, A. Buyuktosunoglu, P. Bose and M. Valero
  • Simulating Whole Supercomuter Applications IEEE Micro Jornal. Vol 31 (3), pp. 32-45, 2011 J. González, M. Casas, M. Moreto, J. Giménez, A. Ramírez, J. Labarta and M. Valero
  • Assessing Accelerator-based HPC Reverse Time Migration – IEEE TPDS, IEEE Transaction on Parallel and Distributed Systems. Vol. 22, No 1, pp. 147-162, Enero 2011 M. Araya-Polo, J. Cabezas, M. Hanzich, M. Pericás, F. Rubio, I. Gelado, M. Shafiq, E. Morancho, N. Navarro, E. Ayguade, J. M. Cela and M. Valero
  • A Highly Scalable Parallel Implementation of H.264 T. HiPEAC Vol.4, pp. 111-134, 2011 A. Azevedo, B. H. H. Juurlink, C. Meenderinck, A. Terechko, J. Hoogerbrugge, M. Alvarez, A. Ramírez and M. Valero
  • The International Exascale Software Project Roadmap IJHPCA, Internnational Journal of High Performance Computer Applications, Vol 25 (1), pp: 3-60, 2011 J. Dongarra, P. H. Beckman, T. Moore, P. Aerts, G. Aloisio, J. C. Andre, D. Barkai, J. Y. Berthou, T. Boku, B. Braunschweig, F. Cappello, B. M. Chapman, X. Chi, A. N. Choudhary, S. S. Dosanjh, T. H. Dunning, S. Fiore, A. Geist, B. Gropp, R. J. Harrison, M. Hereld, M. A. Heroux, A. Hoisie, K. Hotta, Z. Jin, Y. Ishikawa, F. Johnson, S. Kale, R. Kenway, D. E. Keyes, B. Kramer, J. Labarta, A. Lichnewsky, T. Lippert, B. Lucas, B. Maccabe, S. Matsuoka, P. Messina, P. Michielse, B. Mohr, M. S. Müller, W. E. Nagel, H. Nakashima, M. E. Papka, D. A. Reed, M. Sato, E. Seidel, J. Shalf, D. Skinner, M. Snir, T. L. Sterling, R Stevens, F. Streitz, B. Sugar, S. Sumimoto, W. Tang, J. Taylor, R. Thakur, A. E. Trefethen, M. Valero, A. V. Steen, J. S. Vetter, P. Williams, R. W. Wisniewski and K. A. Yelick
  • Hybrid Transactional Memory with Pessimistic Concurrency Control International Journal of Parallel Programming, Vol. 39 (3), pp. 375-396, 2011 E. Vallejo, S. Sanyal, T. Harris, F. Vallejo, R. Beivide, O. Unsal, A. Cristal and M. Valero
  • Exploiting Inter-Task Slack Time of Load Operations for DVFS in Hard Real-Time Multi-Core System SIGBED Review, Vol 8, No.3, pp. 32-35, 2011 E. Quiñones, J. Abella, F. J. Cazorla and M. Valero
  • RMS-TM: a comprehensive benchmark suite for transactional memory systems (abstracts only). SIGMETRICS Performance Evaluation Review 39(3): 19 (2011) G. Kestor, V. Karakostas, O. Unsal, A. Cristal, I. Hur and M. Valero
  • Dynamic Cache Partitioning Based on the MLP of Cache Misses Transactions on High-Performance Embedded Architectures and Compilers III. Lectures Notes on Computer Science, Vol. 6590, pp. 3-23, 2011 M. Moretó, F. J. Cazorla and M. Valero
  • Characterization of Power and Termal Behavior of Power6 System Invited paper. IEEE Journal on Emerging and Selected Topics in Circuits and Systems. Vol. 1, number 3, Septiembre 2011, pp. 228-241 V. Jiménez, F. J. Cazorla, R. Gioiosa, M. Valero, C. Boneti, E. Kursun, C. Y. Cher, C. Isci, A. Buyuktosunoglu and P. Bose
  • Refundar a las Universidades Revista Campus Milenio. México. Febrero, 2011, pp. 8-9.
  • Co-editors of the special Issue: Multicore, the View from Europe IEEE Micro Journal. September- Octubre 2010, pp. 2-4 M. Valero and N. Navarro
  • Utilization Driven Power-Aware Parallel Job Scheduling Computer Science – Research and Development, Springer Verlag, Vol. 25, Numbers 1-2, Mayo 2010, pp. 207-216 M. Etinski, J. Corbalán, J. Labarta and M. Valero
  • On the Problem of Evaluating the Performance of Multiprogrammed Workloads IEEE Transactions on Computers. Vol. 59, no.10, pp. 1722-1728, Diciembre 2010 F. J. Cazorla, A. Pajuelo, O. J. Santana and M. Valero
  • Investigar… per a qué? Revista Informacions de la Universidad Politécnica de Cataluña. Número 226, pp. 2, Enero 2010 M. Valero
  • The International Exascale Software Project: A Call to Cooperative Action by the Global High-Performance Community The International Journal of High Performance Computing Applications. Vol. 23, No. 4, pp. 309-332, Winter 2009 J. Dongarra, P. Beckman, P. Aerts, F. Capello, T. Lippert, S. Matsuoka, P. Messina, T. Moore, R. Stevens, A. Trefethen and M. Valero
  • BSC Vision Towards Exascale The International Journal of High Performance Computing Applications. Vol. 23, No. 4, pp. 340-343, Invierno 2009 J. Labarta, E. Ayguade and M. Valero
  • An Analyzable Memory Controller for Hard Real-Time CMPs IEEE, Embedded Systems Letters 1(4), pp. 86-90, 2009 M. Paolieri, E. Quiñones, F. J. Cazorla and M. Valero
  • Turbocharging Boosted Transactions or: How I Learnt to Stop Worrying and Love Longer Transactions ACM Sigplan Notices 2009;Vol. 44:307-308 C. Kulkarni, O. Unsal, A. Cristal , E. Ayguade and M. Valero
  • FlexDCP: a QoS framework for CMP architectures ACM SIGOPS, Operating Systems review Journal. Special issue on The Interaction Among the OS, the Compiler, and Multicore Processors. Vol. 43, Issue 2, pp. 86-96, Abril 2009 M. Moretó, F. J. Cazorla, A. Ramírez, R. Sakellariou, and M. Valero
  • CPU Accounting in CMP Processors IEEE Computer Architecture Letter. Vol. 9, Issue 1, pp. 17-20, Abril 2009 C. R. Luque, M. Moretó, F. J. Cazorla, R. Giogiosa, A. Buyukstosumoglu and M. Valero
  • Available Task-level Paralellism on the CellBE Scientific Programming Journal, IOS Press. Special Issue on “High Performance Computing with the Cell Broadband Engine”. Vol. 17, Number 1-2, pp. 59-76, 2009 A. Rico, A. Ramírez and M. Valero
  • Performance Evaluation of Macroblock-level Parallelization of H.264 Decoding on a cc-NUMA Multiprocessor Architecture Avances en Sistemas e Informática. Colombia. Vol. 6, No. 1, Junio 2009. ISSN 1657-7663 M. Alvarez,- A. Ramirez, M. Valero, A. Azevedo, C. Meenderinck and B. Juurlink
  • DIA: A Complexity Effective Decoding Architecture IEEE Transaction on Computers, Vol 58, No.4, pp. 448-462, Abril 2009 O. J. Santana, A. Ramírez, A. Falcón and M. Valero
  • ITCA: Inter-Thread Conflict-Aware CPU Accounting for CMPs IEEE Computer Architecture Newsletter. Vol. 8, Issue 1, pp. 17-20, Enero 2009 C. R. Luque, M. Moretó, A. Buyukstosumoglu, F. J. Cazorla, R. Giogiosa, P. Bose and M. Valero
  • Transactional Memory and OpenMP International Journal of Parallel Programming - Sep 2008 M. Milovanovic, R. Ferrrer, O. Unsal, A. Cristal, X. Martorell, E. Ayguadé, J. Labarta and M. Valero
  • A Framework for Managing Multicore Resources IEEE Micro. Special Issue on Interaction of Computer Architecture and Operating Systems in the Multicore Era. Mayo-Junio 2008, Vol. 28, Issue 3, pp. 6-16 K. J. Nesbit, M. Moreto, F. J. Cazorla, A. Ramirez, M. Valero and J. E. Smith
  • Dynamic Cache Partitioning based on the mlp of Cache Misses Transactions on High Performance Embedded Architectures and Compilers, Vol.3, no 1, Marzo, 2008 M. Moretó, F. J. Cazorla, A. Ramirez and M. Valero
  • Nebelung: Execution Environment for Transactional OpenMP International Journal of Parallel Programming. Vol 36, number 3 - Mayo 2008 M. Milovanovic, R. Ferrer, V. Gajinov, O. Unsal, A. Cristal, E. Ayguadé and M. Valero
  • Soft Real-Time Scheduling on SMT Processors with Explicit resource Allocation ARSC 2008, International Conference on Architecture and Computing Systems. Dresden, Germany, Feb. 25-28, 2008. LNCS-4934.ISBN 978-3-540-78152-3. Febrero 2008, pp173-187 C. Boneti, F. J. Cazorla, R. Giogiosa and M. Valero
  • Supercomputing for the Future, Supercomputer for the Past Keynote Lecture. HiPEAC 2008 Conference. High Performance Embedded Architecture Embedded Architectures and Compilers. LNCS 4917, pp. 3-5. Göteborg, Suecia, Enero 2008 M. Valero and J. Labarta
  • Power-efficient VLIW design using clustering and widening IJES, International Journal on Embedded Systems, Vol. 3, No 3, pp. 141-149, 2008 M. Pericás, E. Ayguadé, J. Zalamea, J. Llosa and M. Valero
  • Decoupled State-Execute Architecture LNCS-4759, pp.68-78. Paper from ISHPC-2005. International Symposium on High Performance Computers. Nara, Japón. Septiembre 7-9, 2005. Enero 2008 M. Pericás, A. Cristal, R. González and M. Valero
  • Increasing the Performance of Haskell Software Transactional Memory Trends in Functional Programming, Volume 8, Intellect, 2008 (to appear). ISBN 9781841501963 N. Sonmez, C. Perfumo, S. Stipic, A. Cristal, O. Unsal and M. Valero
  • Exploiting Instruction Locality with a Decoupled kilo-Instruction Processor LNCS-4759, pp. 56-67. Paper from ISHPC-2005. International Symposium on High Performance Computers. Nara, Japón. Septiembre 7-9, 2005. Enero 2008 M. Pericás, A. Cristal, R. González, D. A. Jiménez and M. Valero
  • Workload Characterization and Stateful Networking Aplications LNCS-4759, pp. 130-141. Paper from ISHPC-2005. International Symposium on High Performance Computers. Nara, Japón. Septiembre 7-9, 2005. Enero 2008 J. Verdú, M. Nemirovsky, J. García and M. Valero
  • Multiple Stream Prediction Best paper Award. LNCS, pp. 1-16. Paper from ISHPC-2005. International Symposium on High Performance Computers. Nara, Japan. Septiembre 7-9, 2005. Enero 2008 O. J. Santana, A. Ramírez and M. Valero
  • Enlarging Instruction Streams IEEE Transactions on Computers. Vol 56, No 10, pp. 1342-1357, Octubre, 2007 O. J. Santana, A. Ramírez and M. Valero
  • Transactional Memory: An Overview IEEE-Micro Journal, Vol. 27, No. 3, pp. 8-29, 2007 T. Harris, A. Cristal, O. S. Unsal, E. Ayguadé, F. Gagliardi, B. Smith and M. Valero
  • Energy Saving Through a Simple Load Control Mechanism ACM, Computer Architecture News, pp. 29-36, Vol. 35, Septiembre 2007. Special Issue: Medea 2006 workshop T. Ramirez, A. Pajuelo, O. J. Santana and M. Valero
  • Explaining Dynamic Cache Partitioning Speed Ups IEEE Computer Architecture Letters. Vol. 16, No.1, Marzo 2007 M. Moretó, F. J. Cazorla, A. Ramírez and M. Valero
  • The Impact of Traffic Aggregation on the Memory Performance of Networking Applications Journal of Embedded Computing, pp. 77-82, Vol. 2, no. 1, Octubre 2006 T. Ramirez, A. Pajuelo, O. J. Santana and M. Valero
  • Energy Saving Through a Simple Load Control Mechanism ACM, Computer Architecture News, pp. 29-36, Vol. 35, Septiembre 2007. Special Issue: Medea 2006 workshop T. Ramirez, A. Pajuelo, O. J. Santana and M. Valero
  • Predictable Performance in SMT processors: Synergy Between the OS and SMTs IEEE Transactions on Computers. Volume 55, Number 7. Julio, 2006, pp. 785-799 F. Cazorla, P. M. W. Knijnenburg, R. Sakellariou, E. Fernández, A. Ramirez and M. Valero
  • A DRAM/SRAM Memory Scheme for Fast Packet Buffers IEEE Transactions on Computers. Vol. 55 No. 5, pp. 588-602, Mayo 2006 J. García, M. March, Ll. Cerdá, J. Corbal and M. Valero
  • Speculative Execution for Hiding Memory Latency Computer Architecture News, Vol. 33, No. 3, Junio 2005. Special Issue: MEDEA 2004 Workshop, pp. 49-56 A. Pajuelo, A. González and M. Valero
  • Te Impact of Traffic Aggregation on the Memory Performance of Networking Applications Computer Architecture News, Vol. 33, No. 3, Junio 2005. Special Issue: MEDEA 2004 Workshop, pp.57-62 X. Verdú, M. Nemirosvky, J. García and M. Valero
  • Performance, Power Efficiency and Scalability of Asymmetric Cluster Chip Multiprocessors IEEE CAL, Computer Architecture Letters, Enero-Junio 2006, Volume 5, number 1, pp.14-17 T. Morad, U. Weiser, A. Kolodny, M. Valero and E. Ayguadé
  • Dynamic Memory Interval Test vs. Interprocedural Pointer Analiysis in Multimedia Applications ACM Transactions on Architecture and Code Optimization, TACO Journal. Issue 2, Junio 2005, pp. 199-219 E. Salami and M. Valero
  • Kilo-instruction Processors: Overcoming the Memory Wall IEEE-Micro Journal. Special Issue May/Junio05 Future trends of microprocessors. Vol. 25, No. 13, pp. 48-57, 2005 A. Cristal, O. J. Santana, F. Cazorla, M. Galluzzi, T. Ramírez and M. Valero
  • An Optimized Front-End Physical Register File with Banking and Writeback Filtering Lectures Notes on Computer Science, 3471 on “Power Aware Computer Systems”, pp. 1-14, 2005 M. Pericás, R. González, A. Cristal, A. Veidenbaum and M. Valero
  • Fuzzy Memoization for Floating Point Multimedia Applications IEEE Transactions on Computers. Vol. 54, No 7, Julio 2005, pp. 922-927 C. Álvarez, J. Corbal and M. Valero
  • Software Trace Cache IEEE Transactions on Computers, Volume 54, Number 1, Enero 2005, pp.22-35 A. Ramírez, J. Ll. Larriba and M. Valero
  • Better Branch Prediction Through Prophet/Critic Hybrids IEEE Micro Journal, pp. 80-89. Enero-Febrero, 2005 A. Falcon, J. Stack, A. Ramírez, K. Lai and M. Valero
  • Hardware Support for Early Register Release IJHPCN. International Journal on High Performance and Networking. Vol. 3, No. 2/3, pp. 83-94, 2005 T. Monreal, V. Viñals, A. González and M. Valero
  • Towards Kilo-instruction Processors ACM Transactions on Architecture and Code Optimization, TACO Journal. Vol. 1, No. 4, pp. 389-417, Diciembre 2004 A. Cristal, O. J. Santana, J. Martínez and M. Valero
  • Initial Evaluation of Multimedia Extensions on VLIW Architectures Lectures Notes on Computer Science. Editor Springer-Verlag, Volume 3133, Noviembre 2004 E. Salami and M. Valero
  • Register-constrained Modulo Scheduling IEEE Transactions on Parallel and Distributed Systems, vol. 15, no. 6, Junio 2004 J. Zalamea, J. Llosa, E. Ayguadé and M. Valero
  • A Low-Complexity Fetch Architecture for High-Performance Superscalar Processors ACM Transactions on Architecture and Code Optimization, TACO Journal. vol 1, no. 2, pp 220-245, Junio 2004 O. J. Santana, A. Ramirez, J. L. Larriba-Pey, and M. Valero
  • DCache Warn: An I-Fetch Policy to Increase SMT Efficiency International Journal of Parallel and Distributed Computing, IJPDC. Elsevier Science. Junio 2004, ISBN: 0-7695-2132-0F. J. Cazorla, E. Fernández, A. Ramírez and M. Valero
  • Performance and Power Evaluation of Clustered VLIW Processors with Functional Units Lecture Notes on Computer Science. Editor Springer-Verlag, Volume 3133, Noviembre 2004 M. Pericas, E. Ayguadé, J. Zalamea, J. Llosa and M. Valero
  • Software and Hardware Techniques to Optimize Register File Utilization in VLIW International Journal of Parallel Programming, Vol. 32, No 6, Diciembre, 2004, pp. 447-474 J. Zalamea, J. Llosa, E. Ayguadé and M. Valero
  • Power and Performace Evaluation of Widened and Clustered VLIW Cores LNCS, 2005 (to be published)M. Pericas, E. Ayguadé, J. Zalamea, J. Llosa and M. Valero
  • Late Allocation and Early Release of Physical Registers IEEE Transactions on Computers. Vol. 53, No 10, pp. 1244-1259. Octubre 2004 T. Monreal, V. Viñals, J, González, A. González, M. Valero
  • QoS for High Performance SMT Processors for Embedded Systems IEEE-Micro Journal, Julio-Agosto 2004 F. J. Cazorla, P. M. W. Knijnenburg, R. Sakellariou, E. Fernandez, A. Ramírez and M. Valero
  • Dynamic Memory Instruction Bypassing IJPP, International Joiurnal on Parallel Processing . Plenun Published Corporation. Special issue on selected papers from ICS-2003 (Internatinal Conference on Supercomputing. Vol 32(3), pp.199-224, Mayo 2004 D. Ortega, M. Valero and E. Ayguadé
  • Future ILP Processors IJHPCN. International Journal of High Performance Computing and Networking. Vol. 2, No 1, pp. 1-11, 2004 A. Cristal, D. Ortega, J. Llosa and M. Valero
  • A Partitioned Instruction Queue to Reduce Instruction Wakeup Energy IJHPCN. International Journal of High Performance Computing and Networking. Vol. I, N. 4, pp 153-161 A. Ramírez, A. Cristal, A. V. Veidenbaum, L. Villa and M. Valero
  • High Performance and Low Power VLIW for Numerical Applications IJHPCN. International Journal of High Performance Computing and Networking. Enero 2004, Volumen 1, No 4M. Pericas, E. Ayguadé, J. Zalamea, J. Llosa and M. Valero
  • A Latency-Conscious SMT Branch Prediction Architecture ISHPC-V. IJHPCN. International Journal of High Performance Computing and Networking. Vol. 2, No 1, pp. 11-21, 2004 A. Falcon, O. J. Santana, A. Ramirez and M. Valero
  • Optimizing Long-Latency-Load-Aware Fetch Policies for SMT Processors IJHPCN. International Journal of High Performance Computing and Networking. Vol. 2, No. 1, pp.45-54, 2004 F. J. Cazorla, E. Fernández, A. Ramírez and M. Valero
  • A Case for Resource Conscious Out-of-Order Processor: Towards Kilo-instructions in-flight Processors ACM Computer Architecture News. Special Issue: MEDEA Workshop. Marzo 2004 A. Cristal, J. Martínez. J. Llosa and M. Valero
  • A Case for Resource-conscious Out-of-order Processors IEEE TCCA Computer Architecture Letters. Volume 2, Oct. 2003 A. Cristal, J. F. Martínez, J. Llosa and M. Valero
  • Software Trace Cache at IEEE Transactions on Computer Architecture, Volumen 54, No 1, pp: 22-35, ISSNN: 0018-9340, Enero 2005 A. Ramírez, J. Ll. Larriba and M. Valero
  • Kilo-Instruction Processors Invited Paper. ISHPC-V. LNCS-2858. Lecture Notes on Computer Science. Springer Verlag, pp-10-25. Octubre, 2003 A. Cristal, D. Ortega, J. Llosa and M. Valero
  • A Simple Low-Energy Instruction Wakeup Mechanism ISHPC-V. LNCS-2858. Lecture Notes on Computer Science. Springer Verlag, pp-99-112. Octubre, 2003 A. Ramírez, A. Cristal, A. V. Veidenbaum, L. Villa and M. Valero
  • Power-Performance Trade-Offs in Wide and Clustered VLIW Cores for Numerical Codes ISHPC-V. LNCS-2858. Lecture Notes on Computer Science. Springer Verlag, pp. 113-126. Octubre, 2003 M. Pericas, E. Ayguadé, J. Zalamea, J. Llosa and M. Valero
  • Tolerating Branch Predictor Latency on SMT Processors ISHPC-V. LNCS-2858. Lecture Notes on Computer Science. Springer Verlag, pp.86-98. Octubre, 2003 A. Falcon, O. J. Santana, A. Ramírez and M. Valero
  • Improving Memory Latency Aware Fetch Policies for SMT Processors ISHPC-V. LNCS-2858. Lecture Notes on Computer Science. Springer Verlag, pp-70-85. Octubre, 2003 F. J. Cazorla, E. Fernández, A. Ramírez and M. Valero
  • A Cost-Effective Architecture for Vectorizable Numerical and Multimedia Applications TOCS: Theory of Computing Systems, Vol. 36, pp. 575-593 Sept. 2003. Springer Verlag, Nueva York. ISSN 1432-4350 F. Quintana, J. Corbal, R. Espasa and M. Valero
  • MIRS: Modulo Scheduling with Integrated Register Spilling Languages and Compilers for Parallel Computing. Lecture Notes in Computer Science LNCS 2624, pp. 239-253, Mayo 2003 J. Zalamea, J. Llosa, E. Ayguadé and M. Valero
  • Costo Energético de la Revolución Informática Revista de Libros. Número 65, páginas 30-31. Mayo 2002. ISSN: 1137-2249 M. Valero
  • Errata on Measuring Experimental Error in Microprocessor Simulation ACM Computer Architecture News, Vol. 30, No.1, Marzo 2002, pp.2-4 R. Desikan, D. Bourger, S. W. Keckler, Ll. Cruz, F. Latorre, A. González and M. Valero
  • Software Trace Cache for Commercial Applications IJPP, the International Journal on Parallel Programming. Volumen 30, No 5, pp: 373-395, Octubre 2002A. Ramírez, J.L. Larriba-Pey, C. Navarro, M. Valero and J. Torrellas
  • Initial Results on Fuzzy Floating Point Computation for Multimedia Processors IEEE TCCA Computer Architecture Letters. Volume 1 Enero 2002 C. Alvarez, J. Corbal, E. Salami and M. Valero
  • Parallel Architecture and Compilation Techniques: Selection of Workshop Papers, Guests Editors Introduction ACM Computer Architecture News. Vol. 29, No. 5, Diciembre 2001, pp 9-12 S. Bartolini, R. Giorgi, J. Protic, C.A. Prete and M. Valero
  • Premios Nacionales de Investigación Revista Industría y Minería. Número 346, Dic. 2001, pp. 29-32. Edita Consejo Superior de Colegios de Ingenieros de Minas. ISSN: 1137-8042 M. Valero
  • Instruction Fetch Invited Paper. Proceedings of the IEEE. Special Issue on Microprocessor Architectures and Compiler Technology, Vol 89, Issue 11,Nov. 2001, pp.1588-1609 A. Ramírez, J-L. Larriba and M. Valero
  • Cost-concious Strategies to Increase Performance of Numerical Programs on Aggressive VLIW Architectures IEEE Transactions on Computers. Vol. 50, Issue 10. Octubre 2001, pp. 1033-1051 D. López, J. Llosa, M. Valero and E. Ayguadé
  • Branch Prediction Using Profile Data Lectures Notes in Computer Science 2150 Springer 2001, ISBN 3-540-42495-4 Sep. 2001 A. Ramírez, J. L. Larriba-Pey and M. Valero
  • Multimedia and Embedded Systems Lectures Notes in Computer Science 2150 Springer 2001, ISBN 3-540-42495-4, pp. 651-652 S. Vassiliadis, F. Catthoor, M. Valero and S. Cotofana
  • Early 21 st. Century Processors IEEE Computer Magazine. Special Issue. Guest Editorial, Abril 2001. pp 47-51 S. Vajapeyam and M. Valero
  • Lifetime-sensitive Modulo Scheduling in a Production Environment IEEE Transactions on Computers. Vol. 50, Number 3. Marzo 2001, pp. 234-249 J. Llosa, E. Ayguadé, A. González, M. Valero and J. Eckart
  • International Conference on High-Performance Computing, HiPC-7 Editor. Lectures Notes on Computer Science number 1970. Bangalore, Dic. 2000. ISBN 3-540-41429-0 M. Valero, V. Prasanna and S. Vajapeyam
  • High Performance Computing. Third International Symposium, ISHPC 2000 Editor. Lectures Notes on Computer Science number 1940. Tokyo, Octubre 2000. ISBN 3-540-41128-3 M. Valero, K. Joe, M. Kitsuregawa and H. Tanaka
  • A Stream Processor Front-end IEEE Computer Society Technical Committee on Computer Architecture Newsletter. Junio 2000, pp 10-13 A. Ramírez, J. L. Larriba and M. Valero
  • Dynamic Register Renaming Through Virtual-Physical Registers The Journal of Instruction Level Parallelism, vol.2, Mayo 2000. (http://www.jilp.org/vol2)T. Monreal, A. González, M. Valero, J. González and V. Viñals
  • Computadors per al proper mil.leni Revista TERAFLOP, núm. 45. Oct. 1999, pp. 6-8 M. Valero
  • The Evolution of Cache Memories Special Issue on Cache Memory IEEE, Transactions on Computers. pp. 97-99. Febrero 1999 M. Valero and V. Milutinovic
  • Registers Size Influence on Vector Architectures Lectures Notes on Computer Science, Springer Verlag. Vol. 1573, 1999. pp. 439-451 L. Villa, R. Espasa and M. Valero
  • A Comparison between Superscalar and Vector Processors Lectures Notes in Computer Science, Springer-Verlag. Vol. 1573, 1999. pp. 548-560 F. Quintana, R. Espasa and M. Valero
  • A Simulation Study of Decoupled Vector Architectures Journal of Supercomputing, Kluwer Academic. Vol. 14, number 2, Sep/Octubre 1999, pp. 129-152 R. Espasa and M. Valero
  • Modulo Scheduling with Reduced Register Pressure IEEE Transactions on Computers. Vol. 47, No. 6. Junio 1998, pp. 625-638 J. Llosa, M. Valero, E. Ayguadé and A. González
  • Quantitative Evaluation of Register Pressure on Software Pipeline Loops International Journal of Parallel Programming. Plenum Publishing Corporation. Vol. 26, No 2. Febrero 1998 pp. 121-142 J. Llosa, E. Ayguadé and M. Valero
  • Exploiting Instruction and Data-Level Parallelism IEEE Micro Journal. Vol. 17, No 5, Sep/Octubre 1997, pp. 20-27 R. Espasa and M. Valero
  • Software Management of Selective and Dual Data Caches IEEE Computer Society. Technical Committee on Computer Architecture. Marzo 1997, pp 3-10 F. J. Sánchez, A. González and M. Valero
  • Arquitectura de los Procesadores Mundo Electrónico. Editorial Marcombo. Noviembre 1996, pp. 78-84 M. Valero y A. González
  • Supercomputadores Anuario de Ciencia, Tecnología y Medioambiente. El Pais, 1996, pp. 342-347. ISBN 84-86459-64-8 M. Valero
  • Centro de Computación y Comunicaciones de Cataluña Revista de Física. Editor: Sociedad Catalana de Física. 1er semestre 1996, pp. 40-45 M. Valero
  • Analyzing Reference Patterns in Automatic Data Distribution Tools International Journal of Parallel Programming. Plenum Publishing Corporation. Vol. 23, No 6, Diciembre 1995, pp. 515-535 E. Ayguadé, J. Labarta, J. García, M. Gironès and M. Valero
  • Vector Multiprocessors with Arbitrated Memory Access ACM, Computer Architecture News. Vol. 23, No 2, Mayo 1995, pp 243-252 M. Peiron, M. Valero, E. Ayguadé and T. Lang
  • Increasing the Number of Conflict-Free Vector Access IEEE Transactions on Computers. Vol. 44, No 5, Mayo 1995, pp 634-646 M. Valero, T. Lang, M. Peirón and E. Ayguadé
  • Network Synchronization and out-of-order Access to Vectors Parallel Processing Letters. Diciembre 1994. pp. 405-417. No 4, Vol 4 M. Valero, E. Ayguadé and M. Peirón
  • Synchronized Access to Streams in Multiprocessors IEEE TC on Computer Architecture Newsletter, 1993, pp. 37-41 M. Peirón, M. Valero, E. Ayguadé and T. Lang
  • Arquitectura de los Computadores para Simulación Documentos COTEC sobre oportunidades tecnológicas. Número 3: “Simulación”. Dic. 1993, pp. 32-39 M. Valero, E. Ayguadé
  • Automatic Data-Mapping for Distributed-Memory Multiprocessor Systems International Journal of Mini and Microcomputers. Vol 15, No. 3. 1993, pp. 109-115 J. Torres, E. Ayguadé, J. Labarta, J. M. Llabería and M. Valero
  • Multilevel Orthogonal Blocking for Dense Linear Algebra Computations IEEE TC on Computer Architecture Newsletter. 1993, pp. 10-14 J. J. Navarro, A. Juan, M. Valero, J. M. Llabería and T. Lang
  • Conflict-Free Access to Streams in Multiprocessor Systems Microprocessing and Microprogramming Vol. 38, numbers 1-5, p. 119-130. Sept. 1993 M. Peirón, M. Valero, E. Ayguadé and T. Lang
  • A Method for Implementation of One-Dimensional Systolic Algorithms with Data Contraflows Using Pipelined Functional Units Journal of VLSI Signal Processing. Vol. 4, 1992. Editorial Kluwer Academic Publishers, pp. 7-25 M. Valero-García, J.J. Navarro, J. M. Llabería, M. Valero and T. Lang
  • Increasing the Number of Strides for Conflict-Free Vector Access ACM Computer Architectures News, Mayo 1992, Vol. 20, pp. 372-381 M. Valero, T. Lang, J. M. Llabería, M. Peirón, E. Ayguadé and J. J. Navarro
  • Conflict-Free Strides for Vectors in Matched Memories Parallel Processing Letters. Edit. World Scientific. Vol. 1. No. 2, Diciembre 1991, pp. 95-102 M. Valero, T. Lang, J. M. Llabería, M. Peirón, J. J. Navarro and E. Ayguadé
  • A Block Algorithm and Optimal Fixed-Size Systolic Array Processor for the Algebraic Path Problem Journal of VLSI Signal Processing 1, pp. 153-162. Dic. 1989. Kluwer Academic Publishers, Boston F. Núñez and M. Valero
  • LU Decomposition on a Linear Systolic Array Processor International Journal of Mini and Microcomputers. Vol. 11, No. 1, pp. 4-8, 1989 J. J. Navarro, J. M. Llabería, F. Núñez and M. Valero
  • Proyectos Europeos: Algunas experiencias e ideas relacionadas con ESPRIT Revista Mundo Electrónico. Editorial Marcombo. No. 200. Nov. 1989, pp. 375-379 M. Valero
  • Systematic Adaptation of Systolic Algorithms to the Hardware ACM Computer Architectures News, 1989, pp. 96-104 M. Valero-García, J. J. Navarro, J. M. Llabería and M. Valero
  • Arquitecturas RISC Revista de “Ingeniería: Cálculo, diseño y fabricación”. Hewlett Packard, Vol. 3, Sept. 1988 M. Valero
  • Partitioning: An Essential Issue to Map Algorithms Into Systolic Array Processors Special issue of IEEE Computer Magazine on the Subject: “Systolic Arrays: From Concept to Implementation”. Julio 1987, Vol. 20, No. 7, pp. 77-89 J. J. Navarro, J. M. Llabería and M. Valero
  • A Discrete Optimization Problem in Local Area Networks and Data Aligment IEEE Transactions on Computers. Junio 1987, Vol. C-36, pp.702-713 M. A. Fiol, J. L. Yebra, I. Alegre and M. Valero
  • Supercomputadores Revista Mundo Electrónico. Editorial Marcombo. Dic. 1986, pp. 117-129 M. Valero, J. M. Llabería, J. R. Beivide
  • Computing Size-Independent Matrix Problems on Systolic Array Processors ACM, Comp.Architecture News. Vol. 14, Junio 1986, pp. 271-278 J. J. Navarro, J. M. Llabería and M.Valero
  • Exact an Approximate Models for Multiprocessor Systems with Single Bus and Distributed Memory International Journal of Mini and Microcomputers, Vol. 8, No. 2, pp. 44-48, 1986 E. Sanvicente, M. Valero, T. Lang and I. Alegre
  • Optimization of Double-Loop Structures for Local Networks Int. Journal of Mini and Microcomputers, Vol. 8, No. 2, pp. 40-44, 1986 M. A. Fiol, M. Valero, T. Lang and I. Alegre
  • Analysis and Simulation of Multiplexed Single Bus Networks with and without Buffering ACM, Computer Architecture News. Vol. 13, 1985, pp. 414-421 J. M. Llabería, M. Valero, J. Labarta and E. Herrada
  • Reduced Interconnection Networks Based in the Multiple-Bus for Multiprocessor Systems International Journal of Mini and Microcomputers, Vol. 6, Núm. 1, pp. 4-9, 1984 M. A .Fiol, M. Valero, J. L. Andrés and T. Lang
  • Redes de Interconexión para Sistemas Multiprocesadores Revista Mundo Electrónico. Ed. Marcombo. Sept. 1983, pp. 117-129 M. Valero, E. Sanvicente, J. M. Llabería, J. Labarta
  • A Performance Evaluation of the Multiple-Bus Network for Multiprocessor Systems ACM SIGMETRICS Performance Evaluation Review. Special issue. Agosto 1983, pp. 200-206 M. Valero, E. Sanvicente, J. M. Llabería, T. Lang and J. Labarta
  • Reduction of Connections for Multibus Organization IEEE, Transaction on Computers, Vol. C-32, No. 8, Agosto 1983 T. Lang, M. Valero and M. A. Fiol
  • Optimización de redes locales en doble anillo Revista Mundo Electrónico. Editorial Marcombo. Marzo 1983, pp. 91-99 M. A. Fiol, J. L. Andrés Yebra, I. Alegre, M. Valero
  • Bandwidth of Crossbar and Multibus Connections for Multiprocessors IEEE, Transactions on Computers. Vol. C-31, No. 12, Dic. 1982, pp. 1227-1234 T. Lang, M. Valero and I. Alegre
  • M-users, B-Servers Arbiter for Multibus Multiprocessor Microprocessing and Microprogramming. The Euromicro Journal. Agosto 1982, pp. 1-18 T. Lang and M. Valero
  • Sistemas de Ficheros de Discos Flexibles para Microcomputadores Revista Mundo Electrónico. Ed. Marcombo.pp. 95-103. Nov. 1981 A. Alcalá, M. Valero, C. Rosell, J. Alastruey
  • Arquitectura de los Microprocesadores de 16 bits: Estudio de la familia NS-16000 (2a. parte) Revista Mundo Electrónico. Ed. Marcombo, pp. 120-130, Nov. 1981 M. Valero and D. Vidal
  • Arquitectura de los Microprocesadores de 16 bits: I-8086, Z-8000 y M- 68000 Revista Mundo Electrónico. Editorial Marcombo, pp. 101-117. Diciembre 1980 M. Valero
  • Sistemas Multiprocesador: Características y Posibilidades Revista NOVATICA, pp. 46-58, Nov-Dic. 1979 M. Valero, M. Medina, E. Herrada
  • Sección Micromundo en la revista Mundo Electrónico Editorial Marcombo, durante los meses de Mayo de 1978 a Septiembre de 1978 A. Alabau, M. Valero