Computer Architecture For Parallel Paradigms

Primary tabs

Mostrando 151 - 180 resultados de 228

2008

Why you should profile Transactional Memory Applications on an Atomic Block basis: A Haskell Case Study

N. Sönmez, A. Cristal, O. Unsal, T. Harris, and M. Valero
A Distributed Processor State Management Architecture for Large-Window Processors

I. González, M. Galluzzi, A. Veidenbaum, M. A. Ramírez, A. Cristal, and M. Valero
A distributed processor state management architecture for large-window processors

41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41)

I. González, M. Galluzzi, A. Veidenbaum, M. A. Ramírez, A. Cristal, and M. Valero
WormBench: a configurable workload for evaluating transactional memory systems

9th workshop on MEmory performance: DEaling with Applications, systems and architecture (MEDEA 2008)

F. Zyulkyarov, A. Cristal, S. Cvijic, E. Ayguade, M. Valero, O. Unsal, and T. Harris
Transactional Look-based Parallel Program

Advanced Computer Architecture and Compilation for Embedded Systems. ACACES 2008

G. Kestor, O. Unsal, A. Cristal, and M. Valero
A Two-Level Load/Store Queue Based on Execution Locality

The 35th International Symposium on Computer Architecture (ISCA 2008)

M. Pericas, A. Cristal, F. Cazorla, R. González, A. Veidenbaum, D. A. Jiménez, and M. Valero
The limits of software transactional memory (STM): dissecting Haskell STM applications on a many-core environment

5th Conference on Computing Frontiers

C. Perfumo, N. Sönmez, S. Stipić, O. Unsal, A. Cristal, T. Harris, and M. Valero
Towards Fair Scalable Locking

Workshop on Exploiting Parallelism with Transactional Memory and other Hardware Assisted Methods (EPHAM 2008)

E. Vallejo, S. Sanyal, T. Harris, F. Vallejo, R. Beivide, O. Unsal, A. Cristal, and M. Valero
Hybrid Transactional Memory to accelerate safe lock-based transactions

3rd ACM SIGPLAN Workshop on Transactional Computing (TRANSACT 2008)

E. Vallejo, T. Harris, A. Cristal, O. Unsal, and M. Valero
Nebelung: Execution Environment for Transactional OpenMP

International Journal of Parallel Programming

M. Milovanovic, R. Ferrer, V. Gajinov, O. Unsal, A. Cristal, E. Ayguade, and M. Valero

2007

Low power instructions issue queue design for out of order processors

M. A. Ramírez
Multi-State Processor: Arquitectura sin ROB y con recuperaciones Precisas

II Congreso Español de Informática (CEDI 2007)

I. González, M. Galluzzi, A. Cristal, and M. Valero
Memory Management for Transaction Processing Core in Heterogeneous Chip Multiprocessors

Workshop on Operating System Support for Heterogeneous Multicore Architectures

F. Zyulkyarov, O. Unsal, A. Cristal, M. Milovanovic, E. Ayguade, and M. Valero
Multithreaded software transactional memory and OpenMP

8th MEDEA Workshop Memory Performance: Dealing With Applications, Systems And Architecture (MEDEA 2007)

M. Milovanovic, R. Ferrer, V. Gajinov, O. Unsal, A. Cristal, E. Ayguade, and M. Valero
A Flexible Heterogeneous Multi-Core Architecture

The 2007 International Conference on Parallel Architectures and Compilation Techniques (PACT 2007)

M. Pericas, A. Cristal, F. Cazorla, R. González, D. Jiménez, and M. Valero
Extending C/C++ Language with Atomic Constructs

II Congreso Español de Informática (CEDI 2007)

M. Milovanovic, O. Unsal, A. Cristal, S. Stipić, F. Zyulkyarov, and M. Valero
Increasing the Performance of Haskell Software Transactional Memory

II Congreso Español de Informática (CEDI 2007)

N. Sönmez, C. Perfumo, S. Stipić, A. Cristal, O. Unsal, and M. Valero
Reducing the Activity of Instruction Renaming in Loop Structures

II Congreso Español de Informática (CEDI 2007)

A. García, O. J. Santana, E. Fernández, P. Medina, A. Cristal, and M. Valero
El Procesador Kilo-Ruanahead, una Alternativa para Reducir el Número de Registros Físicos del Procesador Kilo-Instruction

II Congreso Español de Informática (CEDI 2007)

E. Lara, A. Cristal, and M. Valero
Hardware Transactional Memory with Operating System Support, HTMOS

Workshop on Highly Parallel Processing on a Chip in conjunction with Euro-Par

S. Tomić, A. Cristal, O. Unsal, and M. Valero
Implicit Transactional Memory in Kilo-Instruction Multiprocessor

The Twelfth Asia-Pacific Computer Systems Architecture Conference (ACSAC 2007)

M. Galluzzi, E. Vallejo, A. Cristal, F. Vallejo, R. Beivide, P. Stenström, J. E. Smith, and M. Valero
Dissecting Transactional Executions in Haskell

The Second ACM SIGPLAN Workshop on Transactional Computing (TRANSACT 2007)

C. Perfumo, N. Sönmez, O. Unsal, A. Cristal, T. Harris, and M. Valero
The Multi-State Processor

2007 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-07)

I. González, M. Galluzzi, A. Cristal, and M. Valero
Synthetic Workloads for Transactional Memory

2007 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-07)

F. Zyulkyarov, O. Unsal, A. Cristal, and M. Valero
Development and Analysis of the Haskell Transactional Memory Benchmark Suite

2007 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-07)

C. Perfumo, N. Sönmez, A. Cristal, O. Unsal, and M. Valero
Transactional Memory and OpenMP

International Workshop on OpenMP (IWOMP-2007)

M. Milovanovic, R. Ferrer, O. Unsal, A. Cristal, X. Martorell, E. Ayguade, J. Labarta, and M. Valero
UnreadTVar: Extending Haskell Software Transactional Memory for Performance

The 8th Symposium on Trends in Functional Programming (TFP 2007)

N. Sönmez, C. Perfumo, S. Stipić, O. Unsal, A. Cristal, and M. Valero
Compile time support for using transactional memory in C/C++ applications

The 11th Annual Workshop on the Interaction between Compilers and Computer Architecture (INTERACT-11)

M. Milovanovic, O. Unsal, A. Cristal, S. Stipić, F. Zyulkyarov, and M. Valero
Transactional Memory: An Overview

IEEE Micro

T. Harris, A. Cristal, O. Unsal, E. Ayguade, F. Galiardi, B. Smith, and M. Valero

2006

Kilo Instruction Processors

A. Cristal

Páginas