Computer Architecture - Operating Systems (CAOS)

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Mostrando 211 - 240 resultados de 294

2012

Hardware/Software Techniques for Assisted Execution Runtime Systems

The 2nd Workshop on Runtime Environments, Systems, Layering and Virtualized Environments (RESoLVE)

G. Kestor, R. Gioiosa, O. Unsal, A. Cristal, and M. Valero

2011

Energy-Aware Accounting and Billing in Large-Scale Computing Facilities

Micro, IEEE

V.. Jimenez, R.. Gioiosa, F. Cazorla, M. Valero, E.. Kursun, C.. Isci, A.. Buyuktosunoglu, and P.. Bose
Hybrid High-Performance Low-Power and Ultra-Low Energy Reliable Caches

International Conference on Computing Frontiers (CF)

B. Maric, J. Abella, F. Cazorla, and M. Valero
Towards improved survivability in safety-critical systems

International On-Line Testing Symposium (IOLTS)

J. Abella, F. Cazorla, E. Quinones, A. Grasset, S. Yehia, P. Bonnot, D. Gizopoulos, R. Mariani, and G. Bernat
Exploiting Intra-Task Slack Time of Load Operations for DVFS in Hard Real-Time Multi-core Systems

In Work in Progess (WiP), under the the 24nd Euromicro Conference on Real-Time Systems (ECRTS 2011)

E. Quinones, J. Abella, F. Cazorla, and M. Valero
Online Performance Prediction in Processors with DVFS Capabilities

ACACES 2011. Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems

Q. Liu, M. Moreto, J. Abella, and F. Cazorla
Simulating Whole Supercomputer Applications

IEEE Micro

J. González, J. Giménez, M. Casas, M. Moreto, A. Ramirez, J. Labarta, and M. Valero
RVC-based time-predictable faulty caches for safety-critical systems.

IOLTS

J. Abella, E. Quinones, F. Cazorla, M. Valero, and Y. Sazeides
A Case for Energy-Aware Accounting and Billing in Large-Scale Computing Facilities Cost Metrics and Design Implications.

IEEE Micro

V. Jimenez, F. Cazorla, R. Gioiosa, E. Kursun, C. Isci, A. Buyuktosunoglu, P. Bose, and M. Valero
Characterizing Power and Temperature Behavior of POWER6-Based System

IEEE Journal of Emerging and Selected Topics in Circuits and Systems

V. Jimenez, F. Cazorla, R. Gioiosa, M. Valero, C. Boneti, E. Kursun, C. Cher, C. Isci, A. Buyuktosunoglu, and P. Bose
STM2: A Parallel STM for High Performance Simultaneous Multi-Threading Systems

The 20th IEEE International Conference on Parallel Architectures and Compilation Techniques (PACT)

G. Kestor, R. Gioiosa, T. Harris, A. Cristal, O. Unsal, M. Valero, and I. Hur
A Software-Pipelined Approach to Multicore Execution of Timing Predictable Multi-Threaded Hard Real-Time Tasks

M. Paolieri, E. Quinones, J. Wolf, Z. Petrov, F. Cazorla, S. Uhrig, and T. Ungerer
RVC: A Mechanism for Time-Analyzable Real-Time Processors with Faulty Caches

J. Abella, E. Quinones, F. Cazorla, Y. Sazeides, and M. Valero
Efficient runahead threads

T. Ramírez, O. J. Santana, A. Pajuelo, and M. Valero
A Quantitative Analysis of OS Noise

A. Morari, R. Gioiosa, R. Wisniewski, F. Cazorla, and M. Valero
IA3: An Interference Aware Allocation Algorithm for Multicore Hard Real-Time Systems

M. Paolieri, E. Quinones, F. Cazorla, R. I. Davis, and M. Valero

2010

On the Problem of Evaluating the Performance of Multiprogrammed Workloads.

IEEE Transactions on Computers

F. Cazorla, A. Pajuelo, O. J. Santana, E. Fernández, and M. Valero
ITCA: Inter-Task Conflict-Aware CPU Accounting for CMPs

C. Luque, M. Moreto, F. Cazorla, R. Gioiosa, and M. Valero
Hard Real-Time Capable Multicore Processors for Space Applications

M. Moreto, M. Paolieri, J. Abella, E. Quinones, F. Cazorla, and M. Valero
Use of Randomized Caches in Hard Real-Time Systems

6th ACACES 2010 (Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems)

L. Kosmidis, E. Quinones, J. Abella, F. Cazorla, G. Bernat, and E. D. Berger
Load Balancing Using Dynamic Cache Allocation

M. Moreto, F. Cazorla, R. Sakellariou, and M. Valero
Analyzing OS noise for HPC systems

A. Morari, F. Piermaria, E. Betti, R. Gioiosa, and M. Cesati
Using hardware resource allocation to balance