Predictable Parallel Computing

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Mostrando 151 - 180 resultados de 223

2010

Automatic Prefetch and Modulo Scheduling Transformations for the Cell BE Architecture

N. Vujic, M. González, X. Martorell, and E. Ayguade
Decomposable and Responsive Power Models for Multicore Processors using Performance Counters

R. Bertran, M. González, X. Martorell, N. Navarro, and E. Ayguade
5th Int. Conf. on High Performance Embedded Architectures and Compilers (HiPEAC 2010)

Y. N. Patt, P. Foglia, E. Duesterwald, P. Faraboschi, and X. Martorell
Overlapping Communication and Computation by Using a Hybrid MPI/SMPSs Approach

V. Marjanovic, J. Labarta, E. Ayguade, and M. Valero
Scheduling dense linear algebra operations on multicore processors

J. Kurzak, H. Ltaief, J. Dongarra, and R. M. Badia
Scheduling Two-sided Transformations using Tile Algorithms on Multicore Architectures

H. Ltaief, J. Kurzak, J. Dongarra, and R. M. Badia
Cell BE and Bluetooth applied to Digital TV

A. G. Foina, F J. Ramírez-Fernandez, and R. M. Badia
Player Tracker - A Tool to Analyze Sport Players using RFID

A. G. Foina, F J. Ramírez-Fernandez, A. El-Deeb, and R. M. Badia
Task Superscalar: An Out-of-Order Task Pipeline

IEEE/ACM Intl. Symp. on Microarchitecture (MICRO-43)

Y. Etsion, F. Cabarcas, A. Rico, A. Ramirez, R. M. Badia, E. Ayguade, J. Labarta, and M. Valero
DMA++: On the Fly Data Realignment for On-Chip Memories

16th IEEE International Symposium on High-Performance Computer Architecture

N. Vujic, M. González, E. Ayguade, X. Martorell, A. Ramirez, and F. Cabarcas
Task Superscalar: Using Processors as Functional Units

USENIX Workshop on Hot Topics In Parallelism (HotPar)

Y. Etsion, A. Ramirez, R. M. Badia, E. Ayguade, J. Labarta, and M. Valero
Accurate Energy Accounting for Shared Virtualized Environments using PMC-based Power Modeling Techniques

R. Bertran, M. González, Y. Becerra, D. Carrera, V. Beltran, X. Martorell, J. Torres, and E. Ayguade

2009

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