High Performance Domain-Specific Architectures

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Mostrando 1 - 25 resultados de 25

2021

PLANAR: a programmable accelerator for near-memory data rearrangement

ICS '21: 2021 International Conference on SupercomputingProceedings of the ACM International Conference on Supercomputing

H. Zhou, J. Moreira, F. Mueller, Y. Etsion, A. Barredo, A. Armejach, J. Beard, and M. Moretó
Cache-aware Sparse Patterns for the Factorized Sparse Approximate Inverse Preconditioner

Proceedings of the 30th International Symposium on High-Performance Parallel and Distributed Computing (HPDC ’21)

S. Laut, R. Borrell, and M. Casas

2020

Semi-automatic validation of cycle-accurate simulation infrastructures: The case for gem5-x86

Future Generation Computer Systems

J. M.Cebrian, A. Barredo, H. Caminal, M. Moreto, M. Casas, and M. Valero
Improving Predication Efficiency through Compaction/Restoration of SIMD Instructions

Proceedings of the IEEE International Symposium on High Performance Computer Architecture (HPCA)

A. Barredo, J. M. Cebrián, M. Moreto, M. Casas, and M. Valero
Runtime-Guided ECC Protection using Online Estimation of Memory Vulnerability, proceedings

Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis (SC)

L. Jaulmes, M. Moreto, M. Valero, M. Erez, and M. Casas
Evaluating Mixed-Precision Arithmetic for 3D Generative Adversarial Networks to Simulate High Energy Physics Detectors

Proceedings of the 19th IEEE International Conference on Machine Learning and Applications (ICMLA)

J. Osorio, A. Armejach, G. Khattak, E. Petit, S. Vallecorsa, and M. Casas
RICH: Implementing Reductions in the Cache Hierarchy

Proceedings of the 34th ACM International Conference on Supercomputing (ICS'20)

V. Dimić, M. Moreto, M. Casas, J. Ciesko, and M. Valero
Fast gap-affine pairwise alignment using the wavefront algorithmAbstractMotivationResultsAvailability

Bioinformatics

S. Marco-Sola, J. Carlos Moure, M. Moretó, and A. Espinosa
Modeling and optimizing NUMA effects and prefetching with machine learning

Proceedings of the 34th ACM International Conference on Supercomputing (ICS'20)

I. SánchezBarrera, D. Black-Schaffer, M. Casas, M. Moretó, A. Stupnikova, and M. Popov

2018

Low-Precision Floating-Point Schemes for Neural Network Training

M. Ortiz, A. Cristal, E. Ayguadé, and M. Casas

2017

ATM: Approximate Task Memoization in the Runtime System

2017 IEEE International Parallel and Distributed Processing Symposium (IPDPS)

I. Brumar, M. Casas, M. Moreto, M. Valero, and G. S. Sohi
Iteration-Fusing Conjugate Gradient

Proceedings of the 31st ACM International Conference on Supercomputing (ICS)

S. Zhuang, and M. Casas
libPRISM: An Intelligent Adaption of Prefetch and SMT Levels

Proceedings of the 31st ACM International Conference on Supercomputing (ICS)

C. Ortega, M. Moreto, M. Casas, R. Bertran, A. Buyuktosunoglu, A. E. Eichenberger, and P. Bose

2015

Runtime-Guided Management of Scratchpad Memories in Multicore Architectures

2015 International Conference on Parallel Architecture and Compilation (PACT)

L. Alvarez, M. Moreto, M. Casas, E. Castillo, X. Martorell, J. Labarta, E. Ayguade, and M. Valero
Coherence Protocol for Transparent Management of Scratchpad Memories in Shared Memory Manycore Architectures

Proceedings of the 42nd International Symposium on Computer Architecture (ISCA)

L. Alvarez, L. Vilanova, M. Moreto, M. Casas, M. González, X. Martorell, N. Navarro, E. Ayguade, and M. Valero
Exploiting Asynchrony from Exact Forward Recovery for DUE in Iterative Solvers

SC'15 - Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis

L. Jaulmes, M. Casas, M. Moreto, E. Ayguade, J. Labarta, and M. Valero
Evaluating the Impact of OpenMP 4.0 Extensions on Relevant Parallel Workloads

International Workshop on OpenMP (IWOMP)

R. Vidal, M. Casas, M. Moreto, D. Chasapis, R. Ferrer, X. Martorell, E. Ayguade, J. Labarta, and M. Valero
Hardware–Software Coherence Protocol for the Coexistence of Caches and Local Memories

IEEE Transactions On Computers

L. Alvarez, L. Vilanova, M. González, X. Martorell, N. Navarro, and E. Ayguade
Runtime-Aware Architectures

Euro-Par 2015: Parallel Processing

M. Casas, M. Moreto, L. Alvarez, E. Castillo, D. Chasapis, T. Hayes, L. Jaulmes, O. Palomar, O. Unsal, A. Cristal, E. Ayguade, J. Labarta, and M. Valero
A framework for evaluating comprehensive fault resilience mechanisms in numerical programs

Journal of Supercomputing

S. Chen, G. Bronevetsky, B. Li, M. Casas, and L. Peng
Adaptive and application dependent runtime guided hardware prefetcher reconfiguration on the IBM POWER7

6th International Workshop on Adaptive Self-tuning Computing Systems

D. Prat, C. Ortega, M. Casas, M. Moreto, and M. Valero

2014

High level queuing architecture model for high-end processors

D. Roca, M. Nemirovsky, M. Moreto, and M. Casas
Runtime-Aware Architectures: A First Approach

International Journal on Supercomputing Frontiers and Innovations

M. Valero, M. Moreto, M. Casas, E. Ayguade, and J. Labarta
Active Measurement of the Impact of Network Switch Utilization on Application Performance

28th IEEE International Parallel & Distributed Processing Symposium (IPDPS)

M. Casas, and G. Bronevetsky
Active Measurement of Memory Resource Consumption

28th IEEE International Parallel & Distributed Processing Symposium (IPDPS)

M. Casas, and G. Bronevetsky