Jaume Abella Ferrer

2012

• ADAM: An Efficient Data Management Mechanism for Hybrid High and Ultra-Low Voltage Operation Caches

  ACM/IEEE Great Lakes Symposium on VLSI

  B. Maric, J. Abella, and M. Valero
• PROARTIS: Probabilistically Analysable Real-Time Systems

  ACM Transactions on Embedded Computing Systems

  F. Cazorla, E. Quinones, T. Vardanega, L. Cucu-Grosjean, B. Triquet, E. D. Berger, J. Abella, F. Wartel, M. Houston, L. Santinelli, L. Kosmidis, C. Lo, and D. Maxim
• Measurement-Based Probabilistic Timing Analysis for Multi-path Programs

  24th Euromicro Conference on Real-Time Systems (ECRTS 2012)

  L. Cucu-Grosjean, L. Santinelli, M. Houston, C. Lo, T. Vardanega, L. Kosmidis, J. Abella, E. Mezzetti, E. Quinones, and F. Cazorla
• PROARTIS: Probabilistically Analysable Real-Time Systems

  Transactions on Embedded Computing Systems

  F. Cazorla, E. Quinones, T. Vardanega, L. Cucu, B. Triquet, G. Bernat, E. Berger, J. Abella, F. Wartel, M. Houston, L. Santinelli, L. Kosmidis, C. Lo, and D. Maxim

2011

• Hybrid High-Performance Low-Power and Ultra-Low Energy Reliable Caches

  International Conference on Computing Frontiers (CF)

  B. Maric, J. Abella, F. Cazorla, and M. Valero
• Towards improved survivability in safety-critical systems

  International On-Line Testing Symposium (IOLTS)

  J. Abella, F. Cazorla, E. Quinones, A. Grasset, S. Yehia, P. Bonnot, D. Gizopoulos, R. Mariani, and G. Bernat
• Exploiting Intra-Task Slack Time of Load Operations for DVFS in Hard Real-Time Multi-core Systems

  In Work in Progess (WiP), under the the 24nd Euromicro Conference on Real-Time Systems (ECRTS 2011)

  E. Quinones, J. Abella, F. Cazorla, and M. Valero
• Online Performance Prediction in Processors with DVFS Capabilities

  ACACES 2011. Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems

  Q. Liu, M. Moreto, J. Abella, and F. Cazorla
• RVC-based time-predictable faulty caches for safety-critical systems.

  IOLTS

  J. Abella, E. Quinones, F. Cazorla, M. Valero, and Y. Sazeides
• RVC: A Mechanism for Time-Analyzable Real-Time Processors with Faulty Caches

  J. Abella, E. Quinones, F. Cazorla, Y. Sazeides, and M. Valero