PATC Systems workshop: Programming ARM based Prototypes

Date: 11/May/2018 Time: 09:30 - 11/May/2018 Time: 17:30

Target group:   Standard HPC users, some knowledge of multicore and GPU-accelerated systems is desirable, but not required.  

Cost: There is no registration fee. The attendees would need to cover the expenses for travel, accommodation and meals.

Primary tabs


    • Get a comprehensive view of the architecture of the heterogeneous ARM-based platforms deployed in the framework of the Mont-Blanc project, including ARM multicore clusters based on mobile and server technology.
    • Understand the basic concepts of architectural simulations (TaskSim and Gem5)
    • Introduce the MUlti-scale Simulation Architecture, developed within Mont-Blanc 3 for the simulation of next-generation HPC architectures.
    • Study and test simple cases of architectural simulations


High performance computer architecture - The architecture of several ARM-based HPC platforms, deployed and tested during the last four years of research and development within the Mont-Blanc projects will be presented.

Tools for architectural simulation: A complete software stack for performing architectural simulations at scale of thousand of cores will be made available.

Benchmarks and applications analysis – Tracing and architectural parameter study of benchmarks and small applications running on innovative ARM-based platforms will be possible.


Standard HPC users, with some knowledge in ARM CPU/GPU architecture (recommended, but not required).

BSc (or higher) degree in science or engineering with basic knowledge in parallel computing.

We foresee some hands-on session, therefore attendees should bring their own laptop

Level: INTERMEDIATE: for participants with some theoretical and practical knowledge (All courses are designed for specialists with at least 1st cycle degree)









Academic Staff

Barcelona Supercomputing Center on behalf of the Mont-Blanc 3 consortium.

Filippo Mantovani - post-doc at the Barcelona Supercomputing Center (BSC).

Daniel Ruiz - Developer at the Barcelona Supercomputing Center (BSC).

Enrico Calore - post-doc at the University of Ferrara (Italy) and visitor at the Barcelona Supercomputing Center (BSC).



• The User may only download, make and retain a copy of the materials for his/her use for non‐commercial and research purposes.

• The User may not commercially use the material, unless has been granted prior written consent by the Licensor to
do so; and cannot remove, obscure or modify copyright notices, text acknowledging or other means of identification or disclaimers as they appear.

• For further details, please contact BSC‐CNS patc [at] bsc [dot] es

Further information

All PATC Courses at BSC do not charge fees.

Recommended Accomodation: Please follow the link for map of some local hotels.

CONTACT US for further details about MSc, PhD, Post Doc studies, exchanges and collaboration in education and training with BSC.
For further details about Postgraduate Studies in UPC - Barcelona School of Informatics (FiB), visit the website.

Sponsors: BSC and PRACE 4IP project are funding the PATC @ BSC training events.
If you want to learn more about PRACE Project, visit the website.