Severo Ochoa Research Seminars

Tuesday, 27 June, 2017

Wednesday, 14 June, 2017

Speakers:

Short Bio: Daniel A. Jiménez is a Professor in the Department of Computer Science and Engineering at Texas A&M University. He was previously Assistant and later Associate Professor in the Department of Computer Science at Rutgers University, and Professor and Chair of the Department of Computer Science at The University of Texas at San Antonio. Daniel received his doctorate in Computer Sciences from the University of Texas at Austin in 2002.  He is interested in characterizing and exploiting the predictability of programs to improve microarchitecture.  He pioneered the development of neural-inspired branch predictors, which have been implemented in microprocessors from AMD, Oracle, and Samsung.  Daniel designed the neural branch predictor or the Samsung Exynos M1 which is used in the popular Samsung Galaxy S7. He is a Senior Member of the IEEE, an ACM Distinguished Scientist, and an NSF CAREER award winner. He was General Chair of IEEE HPCA in 2011 and Program Chair for IEEE HPCA in 2017.

Monday, 12 June, 2017

This talk will discuss recent technologies that Bruce Jacob and his group have helped to develop in high-performance systems, including Micron’s Hybrid Memory Cube, flash-based main memories, and high-bandwidth/high-capacity memory, and will discuss the impact of tomorrow’s memory technologies on tomorrow’s applications and operating systems.

Wednesday, 07 June, 2017

This talk will cover the technical features of the RISC-V ISA design, which has the goals of scaling from the tiniest implementations for IoT up to the largest warehouse-scale computers, with support for extensive customization. We'll also describe industry-competitive open-source cores developed at UC Berkeley, all written in Chisel, a productive new open-source hardware design language.

Speakers:

Short Bio: Krste Asanović is a Professor in the EECS Department at the University of California, Berkeley. He received a PhD in Computer Science from UC Berkeley in 1998 then joined the faculty at MIT, receiving tenure in 2005.  He returned to join the faculty at Berkeley in 2007, where he co-founded the Berkeley Parallel Computing Laboratory ("Par Lab").
His main research areas are computer architecture, VLSI design, parallel programming and operating system design. He is currently Director of the Berkeley ASPIRE lab tackling the challenge of improving computational efficiency now that transistor scaling is ending.  He leads the free RISC-V ISA project, is Chairman of the RISC-V Foundation, and has recently co-founded SiFive Inc. to support commercial use of RISC-V processors.  He is also an Associate Director at the Berkeley Wireless Research Center, and holds a joint appointment with the Lawrence Berkeley National Laboratory. He received the NSF CAREER award, and is an ACM Distinguished Scientist and an IEEE Fellow.

Thursday, 25 May, 2017

In this lecture, organised in collaboration with UPC, Dr Vargas will explore the key challenges and opportunities for data management in the new scientific world, and discuss how a possible data centric artificial intelligence community can best contribute to these exciting domains.

Thursday, 18 May, 2017

In the Big Data era, due to the ever-growing graph scale and algorithm complexity, several distributed graph processing frameworks have attracted many interests from both academia and industry. In this talk, will be investigated how to achieve the trade-off between performance and cost for large scale graph processing on the Cloud.

Wednesday, 10 May, 2017

Fast content-based searches and complex analytics of the vast amount of data collected via social media, cell phones, ubiquitous smart sensors, and satellites is likely to be the biggest economic driver for the IT industry over the next decade. A cheaper and cooler alternative to large clusters which provides high-performance, high-capacity, scalable random-access flash storage, and allows computation near the data via FPGA-based programmable flash controllers will be presented.

Tuesday, 09 May, 2017

In this talk, a structured approach to the management of HPC resilience using the concept of resilience-based design patterns will be presented. A design pattern is a general repeatable solution to a commonly occurring problem. The authors identify the commonly occurring problems and solutions used to deal with faults, errors and failures in HPC systems.

Tuesday, 28 March, 2017

Prof. Christoph Schär uses emerging heterogeneous supercomputing architectures to accomplish limited-area weather and climate model simulations such as COSMO that is able to run entirely on GPUs (rather than CPUs). Please join us for his presentation on Tuesday March 28th at 12.00, room C6-E101.

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