Severo Ochoa Research Seminars
Monday, 20 November, 2017
This seminar is organized jointly with UPC TelecomBCN school. This session will include two talks from industry leaders in the field of artificial intelligence.
Monday, 23 October, 2017
This seminar is jointly organized with the High Performance Computing research group (CAP) of the Computer Architecture Department at UPC.
Wednesday, 04 October, 2017
Tuesday, 11 July, 2017
The most common software update on the AppStore *by far* is "Bug fixes and performance enhancements." Now that Moore's Law Free Lunch has ended, programmers have to work hard to get high performance for their applications. But why is performance so hard to deliver?
Wednesday, 14 June, 2017
Speakers:
Short Bio: Daniel A. Jiménez is a Professor in the Department of Computer Science and Engineering at Texas A&M University. He was previously Assistant and later Associate Professor in the Department of Computer Science at Rutgers University, and Professor and Chair of the Department of Computer Science at The University of Texas at San Antonio. Daniel received his doctorate in Computer Sciences from the University of Texas at Austin in 2002. He is interested in characterizing and exploiting the predictability of programs to improve microarchitecture. He pioneered the development of neural-inspired branch predictors, which have been implemented in microprocessors from AMD, Oracle, and Samsung. Daniel designed the neural branch predictor or the Samsung Exynos M1 which is used in the popular Samsung Galaxy S7. He is a Senior Member of the IEEE, an ACM Distinguished Scientist, and an NSF CAREER award winner. He was General Chair of IEEE HPCA in 2011 and Program Chair for IEEE HPCA in 2017.
Monday, 12 June, 2017
This talk will discuss recent technologies that Bruce Jacob and his group have helped to develop in high-performance systems, including Micron’s Hybrid Memory Cube, flash-based main memories, and high-bandwidth/high-capacity memory, and will discuss the impact of tomorrow’s memory technologies on tomorrow’s applications and operating systems.
Wednesday, 07 June, 2017
This talk will cover the technical features of the RISC-V ISA design, which has the goals of scaling from the tiniest implementations for IoT up to the largest warehouse-scale computers, with support for extensive customization. We'll also describe industry-competitive open-source cores developed at UC Berkeley, all written in Chisel, a productive new open-source hardware design language.
Speakers:
Short Bio: Krste Asanović is a Professor in the EECS Department at the University of California, Berkeley. He received a PhD in Computer Science from UC Berkeley in 1998 then joined the faculty at MIT, receiving tenure in 2005. He returned to join the faculty at Berkeley in 2007, where he co-founded the Berkeley Parallel Computing Laboratory ("Par Lab").
His main research areas are computer architecture, VLSI design, parallel programming and operating system design. He is currently Director of the Berkeley ASPIRE lab tackling the challenge of improving computational efficiency now that transistor scaling is ending. He leads the free RISC-V ISA project, is Chairman of the RISC-V Foundation, and has recently co-founded SiFive Inc. to support commercial use of RISC-V processors. He is also an Associate Director at the Berkeley Wireless Research Center, and holds a joint appointment with the Lawrence Berkeley National Laboratory. He received the NSF CAREER award, and is an ACM Distinguished Scientist and an IEEE Fellow.