In this talk, a structured approach to the management of HPC resilience using the concept of resilience-based design patterns will be presented. A design pattern is a general repeatable solution to a commonly occurring problem. The authors identify the commonly occurring problems and solutions used to deal with faults, errors and failures in HPC systems.
Prof. Christoph Schär uses emerging heterogeneous supercomputing architectures to accomplish limited-area weather and climate model simulations such as COSMO that is able to run entirely on GPUs (rather than CPUs). Please join us for his presentation on Tuesday March 28th at 12.00, room C6-E101.
This lecture is for BSC staff only.
In this talk Prof. Sifakis will discuss rigorous system design as a formal and accountable process leading from requirements to correct-by-construction implementations.
This time we are honored to present a lecture by Prof. Joseph Sifakis, who was recognized with the prestigious Turing award in 2007 together with Edmund M. Clarke and E. Allen Emerson for their roles in developing model checking into a highly effective verification technology, widely adopted in the hardware and software industries.
Prof. Sifakis´ talk is titled On the Nature of Computing and it is open to everyone. This lecture is organized jointly with FIB as part of the FIB 40th anniversary program.
Speakers:
Joseph Sifakis is Emeritus Senior CNRS Researcher at Verimag. His current research interests cover fundamental and applied aspects of embedded systems design. The main focus of his work is on the formalization of system design as a process leading from given requirements to
trustworthy, optimized and correct-by-construction implementations.
Joseph Sifakis has been a full professor at Ecole Polytechnique Fédérale de Lausanne (EPFL) for the period 2011-2016. He is the founder of the Verimag laboratory in Grenoble, which he directed for 13 years. Verimag is a leading research laboratory in the area of embedded systems, internationally known for the development of the Lustre synchronous language used by the SCADE tool for the design of safety-critical avionics and space applications.
In 2007, Joseph Sifakis has received the Turing Award for his contribution to the theory and application of model checking, the most widely used system verification technique today. Joseph Sifakis has had numerous administrative and managerial responsibilities both at French and European level. He has actively worked to reinvigorate European research in embedded systems as the scientific coordinator of the « ARTIST » European Networks of Excellence, for ten years. He has participated in many major industrial projects led by companies such as Airbus, EADS, France Telecom, Astrium, and STMicroelectronics. Joseph Sifakis is a member of the French Academy of Sciences, a member of the French National Academy of Engineering, a member of Academia Europea, a member of the American Academy of Arts and Sciences, and a member of the National Academy of Engineering. He is a Grand Officer of the French National Order of Merit, a Commander of the French Legion of Honor. He has received the Leonardo da Vinci Medal in 2012. Joseph Sifakis has received in 2009 the Award of the Hellenic Parliament Foundation for Parliamentarism and Democracy. He is a commander of the Greek Order of the Phoenix. He has been the President of the Greek Council for Research and Technology for the period February 2014 – April 2016.
In this Research Seminar we are proud to have two well known speakers: Prof. Wen-Mei Hwu and prof. Avi Mendelson. Wen Mei Hwu will talk about all the recent developments regarding Innovative Applications and Technology Pivots. Avi Mendelson will present a lecture around NVDRAM. During his talk he will discuss what has been done so far and the challenges ahead.
Speakers:
SPEAKER 1
BIO:Wen-mei W. Hwu is a Professor and holds the Sanders-AMD Endowed Chair in the Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign. He directs the IBM-Illinois Center for Cognitive Computing Systems Research Center, serves as the chief scientist of UIUC Parallel Computing Institute and directs the IMPACT research group (www.crhc.uiuc.edu/Impact). He also directs the UIUC CUDA Center of Excellence and serves as one of the principal investigators of the NSF Blue Waters leadership-class supercomputer. For his contributions, he received the ACM SigArch Maurice Wilkes Award, the ACM Grace Murray Hopper Award, the IEEE Computer Society Charles Babbage Award, the ISCA Influential Paper Award, the IEEE Computer Society B. R. Rau Award and the Distinguished Alumni Award in Computer Science of the University of California, Berkeley. He is a fellow of IEEE and ACM. Dr. Hwu received his Ph.D. degree in Computer Science from the University of California, Berkeley.
SPEAKER 2
BIO: Avi Mendelson is a professor in the departments of Electrical Engineering and Computer Science at the Technion. He earned his BSc and MSc degrees from the Computer Science department in the Technion and his PhD degree from the ECE department, University of Massachusetts at Amherst, USA. Prof. Avi Mendelson re-joined Technion recently after spending many years in industry. As part of his industry roles, he was in charge of the first CMP implementation Intel made (Core Due 2), he researched the impact of future SW technologies (such as GPGPU) of future processors and was involved with defining and implementing of many other related technologies such as power management, PCIe-3, memory management unit and more. Avi has more than 60 papers and 18 patents in the field of computer architecture and SW/HW interfaces. Avi has supervised more than 30 doctoral and master degree students, served as an editor of professional journals and was on the program committee of various top conferences. He also served as the program chair of two ICS conferences and the General chair of ISCA’2013 conference. He is member of the ACM Europe council board and serves in the advisory board of HiPEAC (European network of excellence) and has participated in several EU projects including FP7 FET Teraflux and FP7 IP Encore. His main research interests are in the areas of computer architectures, heterogeneous systems (including GPGPU), fault-tolerance systems and operating systems.
Toyotaro Suzumura (IBM) will present a popular data model that naturally represents many problems in the real world.
Speakers:
Bio: Toyotaro Suzumura is a research scientist and technical lead of the Network Science and Big Data Analytics Department at IBM T.J. Watson Research Center in New York, USA as well as a visiting full professor at Barcelona Supercomputing center in Spain, a visiting research scientist at the University of Tokyo.He has broad knowledge and experience in the research and development of computer science including big data processing in large-scale distributed systems, parallel and distributed middleware and its application to real-time data stream computing, large-scale graph processing, cloud computing, and various performance optimization technologies, design and implementation of dynamic scripting language and object-oriented parallel language and large-scale traffic simulation. Dr. Suzumura has been working for IBM Research since 2004 for 13 years after finishing his Ph.D. in 2004. As for his academic career, he had been appointed as a visiting associate professor at Tokyo Institute of Technology since 2009 supervising 16 graduate students in his own laboratory “Suzumura Laboratory” and also a visiting associate professor of University College Dublin in Ireland since 2014/04 supervising 10 master students and 3 Ph.D. students.
Since 2013/10, he has worked for IBM Research – Ireland, the R&D headquarter of IBM Research in Europe as an international assignment specifically focusing on a variety of Smarter-Cities related technologies. Since 2015/04, he joined the headquarter of IBM Research - IBM T.J. Watson Research Center as a full-time research staff member and been leading a team of large-scale graph processing platforms. He has published over 60 reviewed research papers including top-quality international conferences and workshops as well as serving on numerous program committees and as workshop/track/area chair for top-tier conferences. He will be a program chair for IEEE BigData 2017. He is co-principal investigator on Japanese government projects. One of his notable achievements is that he and his team won the first place at the world competition of “Big Data” processing on supercomputers called “Graph500” (http://www.graph500.org) in June 2014, June and November 2015, and June and November 2016.
This year's Christmas lecture is about BSC involvement in the Heidelberg Laureate Forum.The talks and following discussion will present the aims of the HLF and share experiences of BSC researchers that have participated on it. You can discuss with them how to go through the application process and understand the potential benefits of participating in the forum.
Coffee will be served. Registration is required.
Speakers:
Short Bios:
Fabrizio Gagliardi is the Chair of the ACM Europe Policy Committee (EUACM). He works as Distinguished Research Director at the Polytechnic University of Barcelona and serves as Senior Strategy Advisor at the Barcelona Supercomputing Center (BSC), in Spain.
Dr. Gagliardi has been consulting on computing and computing policy matters with the Commission of the European Union, several government and international bodies.
Prior to this and till 2013 he was Europe, Middle East and Africa Director for External Research at Microsoft Research. He joined Microsoft in 2005 after a long career at CERN, the world leading laboratory for particle physics in Geneva. There he held several technical and senior managerial positions since 1975.
Dr. Gagliardi obtained a doctor degree in Computer Science from the University of Pisa in Italy in 1974.
Claudia Rosas got the B.S. degree in computer engineering in 2008 from Universidad Valle del Momboy (Venezuela). She got the M.Sc. in High-Performance Computing in 2009 and the Ph.D. in High-Performance Computing in 2012, both from Universitat Autònoma de Barcelona (Spain). Her research interests include high performance parallel applications, automatic performance analysis and dynamic tuning.
In 2012, she joined as a Post-Doctoral Researcher in the Barcelona Supercomputing Center. Her daily tasks are related to the POP Center of Excellence and the Intel-BSC Exascale Lab, being her main focus the performance analysis of parallel applications for European customers, and the automatic prediction and extrapolation of the expected behaviour of the applications at Exascale Computing.
Paul Carpenter graduated in BA Mathematics (1997) and Diploma in Computer Science (1998) from the University of Cambridge. He received his PhD in computer architecture from the Technical University of Catalonia in 2011. He is currently Senior Researcher at BSC, where he is Principal Investigator of the EUROSERVER and ExaNoDe projects. He is co-chair of the ETP4HPC’s Working Group onprogramming models, WP3 leader for ExaNoDe, WP2 leader for EuroLab-4-HPC, and co-director of five PhD students.
Prior to starting his PhD, he was Senior Software Engineer at ARM in Cambridge, UK, where he was technical lead for audio/video codec development and part of the small team that designed the ARM Advanced SIMD (NEON) vector ISA. He has three worldwide patents. His research interests are server system architecture, energy proportional interconnects, and virtual machine resource sharing.
This month's Severo Ochoa Research Seminar Lecture will be given by Lev Lafayette and Martin Paulo, from the University of Melbourne.
They are visiting a number of European Universities and research institutions to present the Research Platform of the University of Melbourne
Joseph Sifakis is Emeritus Senior CNRS Researcher at Verimag. His current research interests cover fundamental and applied aspects of embedded systems design. The main focus of his work is on the formalization of system design as a process leading from given requirements to
BIO: Wen-mei W. Hwu is a Professor and holds the Sanders-AMD Endowed Chair in the Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign. He directs the IBM-Illinois Center for Cognitive Computing Systems Research Center, serves as the chief scientist of UIUC Parallel Computing Institute and directs the IMPACT research group (www.crhc.uiuc.edu/Impact). He also directs the UIUC CUDA Center of Excellence and serves as one of the principal investigators of the NSF Blue Waters leadership-class supercomputer. For his contributions, he received the ACM SigArch Maurice Wilkes Award, the ACM Grace Murray Hopper Award, the IEEE Computer Society Charles Babbage Award, the ISCA Influential Paper Award, the IEEE Computer Society B. R. Rau Award and the Distinguished Alumni Award in Computer Science of the University of California, Berkeley. He is a fellow of IEEE and ACM. Dr. Hwu received his Ph.D. degree in Computer Science from the University of California, Berkeley.
BIO: Avi Mendelson is a professor in the departments of Electrical Engineering and Computer Science at the Technion. He earned his BSc and MSc degrees from the Computer Science department in the Technion and his PhD degree from the ECE department, University of Massachusetts at Amherst, USA. Prof. Avi Mendelson re-joined Technion recently after spending many years in industry. As part of his industry roles, he was in charge of the first CMP implementation Intel made (Core Due 2), he researched the impact of future SW technologies (such as GPGPU) of future processors and was involved with defining and implementing of many other related technologies such as power management, PCIe-3, memory management unit and more. Avi has more than 60 papers and 18 patents in the field of computer architecture and SW/HW interfaces. Avi has supervised more than 30 doctoral and master degree students, served as an editor of professional journals and was on the program committee of various top conferences. He also served as the program chair of two ICS conferences and the General chair of ISCA’2013 conference. He is member of the ACM Europe council board and serves in the advisory board of HiPEAC (European network of excellence) and has participated in several EU projects including FP7 FET Teraflux and FP7 IP Encore. His main research interests are in the areas of computer architectures, heterogeneous systems (including GPGPU), fault-tolerance systems and operating systems.
