Severo Ochoa Research Seminars

Wednesday, 07 June, 2017
This talk will cover the technical features of the RISC-V ISA design, which has the goals of scaling from the tiniest implementations for IoT up to the largest warehouse-scale computers, with support for extensive customization. We'll also describe industry-competitive open-source cores developed at UC Berkeley, all written in Chisel, a productive new open-source hardware design language.

Short Bio: Krste Asanović is a Professor in the EECS Department at the University of California, Berkeley. He received a PhD in Computer Science from UC Berkeley in 1998 then joined the faculty at MIT, receiving tenure in 2005.  He returned to join the faculty at Berkeley in 2007, where he co-founded the Berkeley Parallel Computing Laboratory ("Par Lab").
His main research areas are computer architecture, VLSI design, parallel programming and operating system design. He is currently Director of the Berkeley ASPIRE lab tackling the challenge of improving computational efficiency now that transistor scaling is ending.  He leads the free RISC-V ISA project, is Chairman of the RISC-V Foundation, and has recently co-founded SiFive Inc. to support commercial use of RISC-V processors.  He is also an Associate Director at the Berkeley Wireless Research Center, and holds a joint appointment with the Lawrence Berkeley National Laboratory. He received the NSF CAREER award, and is an ACM Distinguished Scientist and an IEEE Fellow.

Thursday, 25 May, 2017
In this lecture, organised in collaboration with UPC, Dr Vargas will explore the key challenges and opportunities for data management in the new scientific world, and discuss how a possible data centric artificial intelligence community can best contribute to these exciting domains.
Thursday, 18 May, 2017
In the Big Data era, due to the ever-growing graph scale and algorithm complexity, several distributed graph processing frameworks have attracted many interests from both academia and industry. In this talk, will be investigated how to achieve the trade-off between performance and cost for large scale graph processing on the Cloud.
Wednesday, 10 May, 2017
Fast content-based searches and complex analytics of the vast amount of data collected via social media, cell phones, ubiquitous smart sensors, and satellites is likely to be the biggest economic driver for the IT industry over the next decade. A cheaper and cooler alternative to large clusters which provides high-performance, high-capacity, scalable random-access flash storage, and allows computation near the data via FPGA-based programmable flash controllers will be presented.
Tuesday, 09 May, 2017
In this talk, a structured approach to the management of HPC resilience using the concept of resilience-based design patterns will be presented. A design pattern is a general repeatable solution to a commonly occurring problem. The authors identify the commonly occurring problems and solutions used to deal with faults, errors and failures in HPC systems.
Tuesday, 28 March, 2017
Prof. Christoph Schär uses emerging heterogeneous supercomputing architectures to accomplish limited-area weather and climate model simulations such as COSMO that is able to run entirely on GPUs (rather than CPUs). Please join us for his presentation on Tuesday March 28th at 12.00, room C6-E101.
Friday, 17 March, 2017
This lecture is for BSC staff only. In this talk Prof. Sifakis will discuss rigorous system design as a formal and accountable process leading from requirements to correct-by-construction implementations.
Thursday, 16 March, 2017
This time we are honored to present a lecture by Prof. Joseph Sifakis, who was recognized with the prestigious Turing award in 2007 together with Edmund M. Clarke and E. Allen Emerson for their roles in developing model checking into a highly effective verification technology, widely adopted in the hardware and software industries. Prof. Sifakis´ talk is titled On the Nature of Computing and it is open to everyone. This lecture is organized jointly with FIB as part of the FIB 40th anniversary program.

Joseph Sifakis is Emeritus Senior CNRS Researcher at Verimag. His current research interests cover fundamental and applied aspects of embedded systems design. The main focus of his work is on the formalization of system design as a process leading from given requirements to
trustworthy, optimized and correct-by-construction implementations.
Joseph Sifakis has been a full professor at Ecole Polytechnique Fédérale de Lausanne (EPFL) for the period 2011-2016. He is the founder of the Verimag laboratory in Grenoble, which he directed for 13 years. Verimag is a leading research laboratory in the area of embedded systems, internationally known for the development of the Lustre synchronous language used by the SCADE tool for the design of safety-critical avionics and space applications.
In 2007, Joseph Sifakis has received the Turing Award for his contribution to the theory and application of model checking, the most widely used system verification technique today. Joseph Sifakis has had numerous administrative and managerial responsibilities both at French and European level. He has actively worked to reinvigorate European research in embedded systems as the scientific coordinator of the « ARTIST » European Networks of Excellence, for ten years. He has participated in many major industrial projects led by companies such as Airbus, EADS, France Telecom, Astrium, and STMicroelectronics. Joseph Sifakis is a member of the French Academy of Sciences, a member of the French National Academy of Engineering, a member of Academia Europea, a member of the American Academy of Arts and Sciences, and a member of the National Academy of Engineering. He is a Grand Officer of the French National Order of Merit, a Commander of the French Legion of Honor. He has received the Leonardo da Vinci Medal in 2012. Joseph Sifakis has received in 2009 the Award of the Hellenic Parliament Foundation for Parliamentarism and Democracy. He is a commander of the Greek Order of the Phoenix. He has been the President of the Greek Council for Research and Technology for the period February 2014 – April 2016.


Friday, 17 February, 2017
In this Research Seminar we are proud to have two well known speakers: Prof. Wen-Mei Hwu and prof. Avi Mendelson. Wen Mei Hwu will talk about all the recent developments regarding Innovative Applications and Technology Pivots. Avi Mendelson will present a lecture around NVDRAM. During his talk he will discuss what has been done so far and the challenges ahead.


BIO: Wen-mei W. Hwu is a Professor and holds the Sanders-AMD Endowed Chair in the Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign. He directs the IBM-Illinois Center for Cognitive Computing Systems Research Center, serves as the chief scientist of UIUC Parallel Computing Institute and directs the IMPACT research group ( He also directs the UIUC CUDA Center of Excellence and serves as one of the principal investigators of the NSF Blue Waters leadership-class supercomputer. For his contributions, he received the ACM SigArch Maurice Wilkes Award, the ACM Grace Murray Hopper Award, the IEEE Computer Society Charles Babbage Award, the ISCA Influential Paper Award, the IEEE Computer Society B. R. Rau Award and the Distinguished Alumni Award in Computer Science of the University of California, Berkeley. He is a fellow of IEEE and ACM. Dr. Hwu received his Ph.D. degree in Computer Science from the University of California, Berkeley.


BIO: Avi Mendelson is a professor in the departments of Electrical Engineering and Computer Science at the Technion. He earned his BSc and MSc degrees from the Computer Science department in the Technion and his PhD degree from the ECE department, University of Massachusetts at Amherst, USA. Prof. Avi Mendelson re-joined Technion recently after spending many years in industry. As part of his industry roles, he was in charge of the first CMP implementation Intel made (Core Due 2), he researched the impact of future SW technologies (such as GPGPU) of future processors and was involved with defining and implementing of many other related technologies such as power management, PCIe-3, memory management unit and more. Avi has more than 60 papers and 18 patents in the field of computer architecture and SW/HW interfaces. Avi has supervised more than 30 doctoral and master degree students, served as an editor of professional journals and was on the program committee of various top conferences. He also served as the program chair of two ICS conferences and the General chair of ISCA’2013 conference. He is member of the ACM Europe council board and serves in the advisory board of HiPEAC (European network of excellence) and has participated in several EU projects including FP7 FET Teraflux and FP7 IP Encore. His main research interests are in the areas of computer architectures, heterogeneous systems (including GPGPU), fault-tolerance systems and operating systems.