Francisco Javier Cazorla Almeida

2007

• A Flexible Heterogeneous Multi-Core Architecture

  The 2007 International Conference on Parallel Architectures and Compilation Techniques (PACT 2007)

  M. Pericas, A. Cristal, F. Cazorla, R. González, D. Jiménez, and M. Valero
• Measuring the Performance of Multithreaded Processors

  J. Vera, F. Cazorla, A. Pajuelo, O. J. Santana, E. Fernández, and M. Valero
• On the Problem of Minimizing Workload Execution Time in SMT Processors

  International Conference on Embedded Computer Systems: Architectures, Modelling, and Simulation (SAMOS VII)

  F. Cazorla, P. Knijnenburg, R. Sakellariou, E. Fernández, A. Ramirez, and M. Valero
• FAME: FAirly MEasuring Multithreaded Architectures

  J. Vera, F. Cazorla, A. Pajuelo, O. J. Santana, E. Fernández, and M. Valero
• Online Prediction of Throughput for Different Cache Sizes

  XVIII Jornadas de Paralelismo

  M. Moreto, F. Cazorla, A. Ramirez, and M. Valero
• MLP-aware dynamic cache partitioning

  International Conference on Parallel Architectures and Compilation Techniques (PACT)

  M. Moreto, F. Cazorla, A. Ramirez, and M. Valero
• Explaining Dynamic Cache Partitioning Speed Ups

  IEEE Computer Architecture Letters

  M. Moreto, F. Cazorla, A. Ramirez, and M. Valero
• Online Prediction of Applications Cache Utility

  International Symposium on Systems, Architectures, MOdeling and Simulation (SAMOS)

  M. Moreto, F. Cazorla, A. Ramirez, and M. Valero
• Core to Memory Interconnection Implications for Forthcoming On-Chip Multiprocessors

  1st Workshop on Chip Multiprocessor Memory Systems and Interconnects (CMP-MSI 2007)

  C. Acosta, F. Cazorla, A. Ramirez, and M. Valero

2006

• Boosting ILP{&}TLP with the Flexible Multi-Core (FMC)

  2006 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-06)

  M. Pericas, A. Cristal, R. González, F. Cazorla, D. A. Jiménez, and M. Valero