Francisco Javier Cazorla Almeida

2008

• Architecture performance prediction using evolutionary artificial neural networks

  P. A. Castillo, A. M. Mora, J J. Merelo, J L. Laredo, M. Moreto, F. Cazorla, M. Valero, and S. A. McKee
• MLP-aware dynamic cache partitioning

  2008 International Conference on High Performance Embedded Architectures & Compilers (HiPEAC 2008)

  M. Moreto, F. Cazorla, A. Ramirez, and M. Valero
• Evolutionary system for prediction and optimization of hardware architecture performance

  P. A. Castillo, J J. Merelo, M. Moreto, F. Cazorla, M. Valero, A. M. Mora, J L. Laredo, and S. A. McKee
• Understanding the overhead of the spin-lock loop in CMT architectures

  V. Cakarevic, P. Radojkovic, J. Verdú, A. Pajuelo, R. Gioiosa, F. Cazorla, M. Nemirovsky, and M. Valero
• A two-level Load/Store Queue based on Execution Locality

  M. Pericas, R. González, F. Cazorla, A. Cristal, A. Veidenbaum, D. A. Jiménez, and M. Valero
• Selection of the Register File Size and the Resource Allocation Policy on SMT Processors

  J. J. Alastruey, F. Cazorla, T. Monreal, V. Viñals, and M. Valero
• Measuring Operating System Overhead on CMT Processors

  P. Radojkovic, V. Cakarevic, J. Verdú, A. Pajuelo, R. Gioiosa, F. Cazorla, M. Nemirovsky, and M. Valero
• A Dynamic Scheduler for Balancing HPC Applications

  C. Boneti, R. Gioiosa, F. Cazorla, and M. Valero
• Software-Controlled Priority Characterization of POWER5 Processor

  International Symposium on Computer Architecture (ISCA)

  C. Boneti, F. Cazorla, R. Gioiosa, C-Y. Cher, A. Buyuktosunoglu, and M. Valero
• Balancing HPC Applications Through Smart Allocation of Resources in MT Processors

  C. Boneti, F. Cazorla, R. Gioiosa, J. Corbalán, J. Labarta, and M. Valero