Francisco Javier Cazorla Almeida

2015

• Randomized Caches Can Be Pretty Useful to Hard Real-Time Systems

  LITES

  E. Mezzetti, M. Ziccardi, T. Vardanega, J. Abella, E. Quinones, and F. Cazorla
• PACO: Fast Average-Performance Estimation for Time-Randomized Caches

  2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC)

  S. Milutinovic, E. Quinones, J. Abella, and F. Cazorla
• WCET Analysis Methods: Pitfalls and Challenges on their Trustworthiness

  10th IEEE International Symposium on Industrial Embedded Systems (SIES)

  J. Abella, C. Hernández, E. Quinones, F. Cazorla, P. Ryan Conmy, M. Azkarate-askasua, J. Perez, E. Mezzetti, and T. Vardanega
• CAP: Communication-aware Allocation Algorithm for Real-Time Parallel Applications on Many-cores

  18th Euromicro Conference on Digital System Design (DSD) Madeira, Portugal

  M. Panic, E. Quinones, C. Hernández, J. Abella, and F. Cazorla
• Enabling TDMA Arbitration in the Context of MBPTA

  18th Euromicro Conference on Digital System Design (DSD) Madeira, Portugal

  M. Panic, J. Abella, C. Hernández, E. Quinones, T. Ungerer, and F. Cazorla
• IEC-61508 SIL 3-compliant Pseudo-Random Number Generators for Probabilistic Timing Analysis

  18th Euromicro Conference on Digital System Design (DSD) Madeira, Portugal

  I. Agirre, M. Azkarate-askasua, J. Perez, C. Hernández, J. Abella, T. Vardanega, and F. Cazorla
• A safety concept for a railway mixed-criticality embedded system based on multicore partitioning

  13th IEEE International Conference on Dependable, Autonomic and Secure Computing (DASC-2015)

  I. Agirre, M. Azkarate-askasua, A. Larrucea, J. Perez, T. Vardanega, and F. Cazorla
• EPC: Extended Path Coverage for Measurement-based Probabilistic Timing Analysis

  IEEE Real-Time Systems Symposium (RTSS) San Antonio, Texas

  M. Ziccardi, E. Mezzetti, T. Vardanega, J. Abella, and F. Cazorla
• Increasing Confidence on Measurement-Based Contention Bounds for Real-Time Round-Robin Buses

  Design Automation Conference (DAC) San Francisco, CA

  G. Fernandez, J. Jalle, J. Abella, E. Quinones, T. Vardanega, and F. Cazorla
• Resource Usage Templates and Signatures for COTS Multicore Processors

  DAC '15 Proceedings of the 52nd Annual Design Automation Conference

  G. Fernandez, J. Jalle, J. Abella, E. Quinones, T. Vardanega, and F. Cazorla