Marc Casas

2016

• Evaluation of HPC Applications’ Memory Resource Consumption via Active Measurement

  IEEE Transactions on Parallel & Distributed Systems

  M. Casas, and G. Bronevetsky
• MUSA: A Multi-level Simulation Approach for Next-generation HPC Machines

  Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis

  T. Grass, C. Allande, A. Armejach, A. Rico, E. Ayguade, J. Labarta, M. Valero, M. Casas, and M. Moreto
• POSTER: Exploiting Asymmetric Multi-Core Processors with Flexible System Sofware

  Proceedings of the 2016 International Conference on Parallel Architectures and Compilation - PACT '16

  K. Chronaki, M. Moreto, M. Casas, A. Rico, R. M. Badia, E. Ayguade, J. Labarta, and M. Valero
• Reducing Cache Coherence Traffic with Hierarchical Directory Cache and NUMA-Aware Runtime Scheduling

  Proceedings of the 2016 International Conference on Parallel Architectures and Compilation - PACT '16

  P. Caheny, M. Casas, M. Moreto, H. Gloaguen, M. Saintes, E. Ayguade, J. Labarta, and M. Valero
• CATA: Criticality Aware Task Acceleration for Multicore Processors

  2016 IEEE International Parallel and Distributed Processing Symposium (IPDPS)

  E. Castillo, M. Moreto, M. Casas, L. Alvarez, E. Vallejo, K. Chronaki, R. M. Badia, J. Luis Bosque, R. Beivide, E. Ayguade, J. Labarta, and M. Valero
• Runtime-Guided Mitigation of Manufacturing Variability in Power-Constrained Multi-Socket NUMA Nodes

  ICS '16 Proceedings of the 2016 International Conference on Supercomputing

  D. Chasapis, M. Casas, M. Moreto, M. Schulz, E. Ayguade, J. Labarta, and M. Valero
• TaskPoint: Sampled simulation of task-based programs

  Performance Analysis of Systems and Software (ISPASS), 2016 IEEE International Symposium on

  T. Grass, A. Rico, M. Casas, M. Moreto, and E. Ayguade

2015

• Runtime-Guided Management of Scratchpad Memories in Multicore Architectures

  2015 International Conference on Parallel Architecture and Compilation (PACT)

  L. Alvarez, M. Moreto, M. Casas, E. Castillo, X. Martorell, J. Labarta, E. Ayguade, and M. Valero
• Coherence Protocol for Transparent Management of Scratchpad Memories in Shared Memory Manycore Architectures

  Proceedings of the 42nd International Symposium on Computer Architecture (ISCA)

  L. Alvarez, L. Vilanova, M. Moreto, M. Casas, M. González, X. Martorell, N. Navarro, E. Ayguade, and M. Valero
• Exploiting Asynchrony from Exact Forward Recovery for DUE in Iterative Solvers

  SC'15 - Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis

  L. Jaulmes, M. Casas, M. Moreto, E. Ayguade, J. Labarta, and M. Valero