Marc Casas

2017

• Iteration-Fusing Conjugate Gradient

  Proceedings of the 31st ACM International Conference on Supercomputing (ICS)

  S. Zhuang, and M. Casas
• libPRISM: An Intelligent Adaption of Prefetch and SMT Levels

  Proceedings of the 31st ACM International Conference on Supercomputing (ICS)

  C. Ortega, M. Moreto, M. Casas, R. Bertran, A. Buyuktosunoglu, A. E. Eichenberger, and P. Bose

2016

• PARSECSs: Evaluating the Impact of Task Parallelism in the PARSEC Benchmark Suite

  ACM Transactions on Architecture and Code Optimization

  D. Chasapis, M. Casas, M. Moreto, R. Vidal, E. Ayguade, J. Labarta, and M. Valero
• Task Scheduling Techniques for Asymmetric Multi-core Systems

  IEEE Transactions on Parallel and Distributed Systems

  K. Chronaki, A. Rico, M. Casas, M. Moreto, R. M. Badia, E. Ayguade, J. Labarta, and M. Valero
• Evaluation of HPC Applications’ Memory Resource Consumption via Active Measurement

  IEEE Transactions on Parallel & Distributed Systems

  M. Casas, and G. Bronevetsky
• MUSA: A Multi-level Simulation Approach for Next-generation HPC Machines

  Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis

  T. Grass, C. Allande, A. Armejach, A. Rico, E. Ayguade, J. Labarta, M. Valero, M. Casas, and M. Moreto
• POSTER: Exploiting Asymmetric Multi-Core Processors with Flexible System Sofware

  Proceedings of the 2016 International Conference on Parallel Architectures and Compilation - PACT '16

  K. Chronaki, M. Moreto, M. Casas, A. Rico, R. M. Badia, E. Ayguade, J. Labarta, and M. Valero
• Reducing Cache Coherence Traffic with Hierarchical Directory Cache and NUMA-Aware Runtime Scheduling

  Proceedings of the 2016 International Conference on Parallel Architectures and Compilation - PACT '16

  P. Caheny, M. Casas, M. Moreto, H. Gloaguen, M. Saintes, E. Ayguade, J. Labarta, and M. Valero
• CATA: Criticality Aware Task Acceleration for Multicore Processors

  2016 IEEE International Parallel and Distributed Processing Symposium (IPDPS)

  E. Castillo, M. Moreto, M. Casas, L. Alvarez, E. Vallejo, K. Chronaki, R. M. Badia, J. Luis Bosque, R. Beivide, E. Ayguade, J. Labarta, and M. Valero
• Runtime-Guided Mitigation of Manufacturing Variability in Power-Constrained Multi-Socket NUMA Nodes

  ICS '16 Proceedings of the 2016 International Conference on Supercomputing

  D. Chasapis, M. Casas, M. Moreto, M. Schulz, E. Ayguade, J. Labarta, and M. Valero