Mateo Valero Cortes

2016

• Task Scheduling Techniques for Asymmetric Multi-core Systems

  IEEE Transactions on Parallel and Distributed Systems

  K. Chronaki, A. Rico, M. Casas, M. Moreto, R. M. Badia, E. Ayguade, J. Labarta, and M. Valero
• MUSA: A Multi-level Simulation Approach for Next-generation HPC Machines

  Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis

  T. Grass, C. Allande, A. Armejach, A. Rico, E. Ayguade, J. Labarta, M. Valero, M. Casas, and M. Moreto
• DReAM: An Approach to Estimate per-Task DRAM Energy in Multicore Systems

  ACM Transactions on Design Automation of Electronic Systems

  Q. Liu, M. Moreto, J. Abella, F. Cazorla, and M. Valero
• Network unfairness in dragonfly topologies

  The Journal of Supercomputing

  P. Fuentes, E. Vallejo, C. Camarero, R. Beivide, and M. Valero
• POSTER: Exploiting Asymmetric Multi-Core Processors with Flexible System Sofware

  Proceedings of the 2016 International Conference on Parallel Architectures and Compilation - PACT '16

  K. Chronaki, M. Moreto, M. Casas, A. Rico, R. M. Badia, E. Ayguade, J. Labarta, and M. Valero
• Reducing Cache Coherence Traffic with Hierarchical Directory Cache and NUMA-Aware Runtime Scheduling

  Proceedings of the 2016 International Conference on Parallel Architectures and Compilation - PACT '16

  P. Caheny, M. Casas, M. Moreto, H. Gloaguen, M. Saintes, E. Ayguade, J. Labarta, and M. Valero
• Future Vector Microprocessor Extensions for Data Aggregations

  2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA)

  T. Hayes, O. Palomar, O. Unsal, A. Cristal, and M. Valero
• CATA: Criticality Aware Task Acceleration for Multicore Processors

  2016 IEEE International Parallel and Distributed Processing Symposium (IPDPS)

  E. Castillo, M. Moreto, M. Casas, L. Alvarez, E. Vallejo, K. Chronaki, R. M. Badia, J. Luis Bosque, R. Beivide, E. Ayguade, J. Labarta, and M. Valero
• A Fully Parameterizable Low Power Design of Vector Fused Multiply-Add Using Active Clock-Gating Techniques

  ISLPED '16 Proceedings of the 2016 International Symposium on Low Power Electronics and Design

  I. Ratković, O. Palomar, M. Stanic, O. Unsal, A. Cristal, and M. Valero
• Performance analysis of a hardware accelerator of dependence management for task-based dataflow programming models

  2016 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)

  X. Tan, J. Bosch, D. Jiménez-González, C. Alvarez-Martinez, E. Ayguade, and M. Valero