Osman Unsal

2011

• RMS-TM: A Comprehensive Benchmark Suite for Transactional Memory Systems

  International Conference on Performance Engineering (ICPE 2011)

  G. Kestor, V. Karakostas, O. Unsal, A. Cristal, I. Hur, and M. Valero
• From Plasma to BeeFarm: Design Experience of an FPGA-based Multicore Prototype

  The 7th International Symposium on Applied Reconfigurable Computing (ARC 2011)

  N. Sönmez, O. Arcas, G. Sayilar, A. Cristal, I. Hur, O. Unsal, S. Singh, and M. Valero
• Circuit Design of a Dual-Versioning L1 Data Cache

  Integration The VLSI Journal

  A. Seyedi, A. Armejach, A. Cristal, O. Unsal, I. Hur, and M. Valero
• TMbox: A Flexible and Reconfigurable 16-core Hybrid Transactional Memory System

  The 19th Annual IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM 2011)

  N. Sönmez, O. Arcas, O. Pflucker, A. Cristal, O. Unsal, I. Hur, S. Singh, and M. Valero
• STM2: A Parallel STM for High Performance Simultaneous Multi-Threading Systems

  The 20th IEEE International Conference on Parallel Architectures and Compilation Techniques (PACT)

  G. Kestor, R. Gioiosa, T. Harris, A. Cristal, O. Unsal, M. Valero, and I. Hur

2010

• The Velox Transactional Memory Stack

  Micro, IEEE

  P. Felber, E. Rivière, W. M. Moreira, D. Harmanci, P. Marlier, S. Diestelhorst, M. Hohmuth, M. Pohlack, A. Cristal, I. Hur, O. Unsal, P. Stenström, A. Dragojevic, R. Guerraoui, M. Kapalka, V. Gramoli, U. Drepper, S. Tomić, Y. Afek, G. Korland, N. Shavit, C. Fetzer, M. Nowack, and T. Riegel
• ShadowHTM: Using a dual-bitcell L1 Data Cache to Improve Hardware Transactional Memory Performance

  A. Armejach, A. Seyedi, R T. J. Gil, I. Hur, O. Unsal, A. Cristal, and M. Valero
• Architectural Support for Fair Reader-Writer Locking

  International Symposium on Microarchitecture

  E. Vallejo, R. Beivide, A. Cristal, T. Harris, F. Vallejo, O. Unsal, and M. Valero
• RMS-TM: A challenging transactional memory benchmark suite

  Advanced Computer Architecture and Computation for Embedded Systems (ACACES 2010)

  V. Karakostas, G. Kestor, O. Unsal, A. Cristal, I. Hur, and M. Valero
• FaulTM: Fault-Tolerance Using Hardware Transactional Memory

  Workshop on Parallel Execution of Sequential Programs on Multi-core Architecture (PESPMA)

  G. Yalcin, O. Unsal, I. Hur, and A. Cristal