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2010

An Asymmetric Distributed Shared Memory Model for Heterogeneous Parallel Systems

ACM SIGARCH Computer Architecture News - ASPLOS '10

I. Gelado, J. E. Stone, J. Cabezas, S. Patel, N. Navarro, and W-mei. Hwu
Automatic Prefetch and Modulo Scheduling Transformations for the Cell BE Architecture

N. Vujic, M. González, X. Martorell, and E. Ayguade
Decomposable and Responsive Power Models for Multicore Processors using Performance Counters

R. Bertran, M. González, X. Martorell, N. Navarro, and E. Ayguade
5th Int. Conf. on High Performance Embedded Architectures and Compilers (HiPEAC 2010)

Y. N. Patt, P. Foglia, E. Duesterwald, P. Faraboschi, and X. Martorell
Overlapping Communication and Computation by Using a Hybrid MPI/SMPSs Approach

V. Marjanovic, J. Labarta, E. Ayguade, and M. Valero
Scheduling dense linear algebra operations on multicore processors

J. Kurzak, H. Ltaief, J. Dongarra, and R. M. Badia
Scheduling Two-sided Transformations using Tile Algorithms on Multicore Architectures

H. Ltaief, J. Kurzak, J. Dongarra, and R. M. Badia
Cell BE and Bluetooth applied to Digital TV

A. G. Foina, F J. Ramírez-Fernandez, and R. M. Badia
Player Tracker - A Tool to Analyze Sport Players using RFID

A. G. Foina, F J. Ramírez-Fernandez, A. El-Deeb, and R. M. Badia
G-means Improved for Cell BE Environment

A. G. Foina, R. M. Badia, and F J. Ramírez-Fernandez

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