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2016

Adaptive Runtime-Assisted Block Prefetching on Chip-Multiprocessors

International Journal of Parallel Programming

V. Garcia, A. Rico, C. Villavieja, P. Carpenter, N. Navarro, and A. Ramirez

2014

Adaptive Runtime-Assisted Block Prefetching on Chip-Multiprocessors

Third International Workshop On-chip memory hierarchies and interconnects: organization, management and implementation

V. Garcia, A. Rico, C. Villavieja, P. Carpenter, N. Navarro, and A. Ramirez

2013

The Low Power Architecture Approach Towards Exascale Computing

Journal of Computational Science

N. Rajovic, L. Vilanova, C. Villavieja, N. Puzovic, and A. Ramirez
The low-power architecture approach towards exascale computing

Journal of Computational Science

N. Rajovic, N. Puzovic, L. Vilanova, C. Villavieja, and A. Ramirez

2012

Hardware and Software Support for Distributed Shared Memory in Chip Multiprocessors

C. Villavieja
On the Simulation of Large-scale Architectures Using Multiple Application Abstraction Levels

ACM Transactions on Architecture and Code Optimization

A. Rico, F. Cabarcas, C. Villavieja, M. Pavlovic, A. Vega, Y. Etsion, A. Ramirez, and M. Valero

2011

DiDi: Mitigating The Performance Impact of TLB Shootdowns Using A Shared TLB Directory

Parallel Architectures and Compilation Techniques (PACT)

C. Villavieja, V. Karakostas, L. Vilanova, Y. Etsion, A. Ramirez, A. Mendelson, N. Navarro, A. Cristal, and O. Unsal
The low-power Architecture Approach Towards Exascale Computing

Workshop on Latest Advances in Scalable Algorithms for Large-Scale Systems (ScalA)

N. Rajovic, N. Puzovic, L. Vilanova, C. Villavieja, and A. Ramirez
FELI: HW/SW support for On-Chip Distributed Shared Memory in Multicores

Euro-Par

C. Villavieja, Y. Etsion, A. Ramirez, and N. Navarro

2008

On-Chip memories, the OS perspective

5th HiPEAC Industrial Workshop

C. Villavieja, I. Gelado, A. Ramirez, and N. Navarro

Pàgines