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2013

A Proposal for Task-Generating Loops in OpenMP

9th International Workshop on OpenMP (IWOMP)

X. Teruel, M. Klemm, K. Li, X. Martorell, S. Olivier, and C. Terboven
Resource-aware task scheduling.

4th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures (PARMA)

M. Tillenius, E. Larsson, R. M. Badia, and X. Martorell
Heterogeneous tasking on SMP/FPGA SoCs: the case of OmpSs and the Zynq

21st IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)

A. Filgueras, E. Gil, C. Álvarez, D. Jiménez, X. Martorell, J. Langer, and J. Noguera
Improving Performance of All-to-all Communication Through Loop Scheduling in PGAS Environments

27th International Conference on Supercomputing (ICS)

M. Alvanos, T. Gabriel, M. Farreras, E. Tiotto, J N. Amaral, and X. Martorell
Improving Communication in PGAS Environments: Static and Dynamic Coalescing in UPC

27th International Conference on Supercomputing (ICS)

M. Alvanos, M. Farreras, E. Tiotto, J N. Amaral, and X. Martorell
Implementing OmpSs Support for Regions of Data in Architectures with Multiple Address Spaces

27th International Conference on Supercomputing (ICS)

J. Bueno-Hedo, R. M. Badia, X. Martorell, E. Ayguade, and J. Labarta
Rendering of Bezier surfaces on handheld devices

Journal of WSCG (Plzen, Print)

R C. Figueroa, M A. Lopez, E J P. Gonzalez, M. Gil, and X. Martorell
Counter-Based Power Modeling Methods: Top-Down vs. Bottom-Up

Computer Journal

R. Bertran, M. González, X. Martorell, N. Navarro, and E. Ayguade
A Systematic Methodology to Generate Decomposable and Responsive Power Models for CMPs

IEEE Transactions on Computers

R. Bertran, M. González, X. Martorell, N. Navarro, and E. Ayguade
Heterog eneous tasking on SMP/FPGA SoCs: the case of OmpSs and the Zynq

workshop @VLSI-SOC: W1A (Special Session 2): Are processors the NAND gats of the future?

A. Filgueras, E. Gil, C. Álvarez, D. Jiménez-González, X. Martorell, J. Langer, and J. Noguera

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