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2012

Autonomic Placement of Mixed Batch and Transactional Workloads

IEEE Transactions on Parallel and Distributed Systems

D. Carrera, M. Steinder, I. Whalley, J. Torres, and E. Ayguade

2011

Integrating dataflow abstractions into transactional memory

Systems for Future Multi-Core Architectures (SFMA'11)

V. Gajinov, A. Cristal, M. Milovanovic, E. Ayguade, O. Unsal, and M. Valero
Mercurium: Design Decisions for a S2S Compiler

Cetus Users and Compiler Infastructure Workshop in conjunction with PACT 2011

R. Ferrer, S. Royuela, D. Caballero, A. Duran, X. Martorell, and E. Ayguade
Poster: programming clusters of GPUs with OMPSs

Proceedings of the international conference on Supercomputing

J. Bueno, A. Duran, X. Martorell, E. Ayguade, R. M. Badia, and J. Labarta
Implementation of a Reverse Time Migration Kernel using the HCE High Level Synthesis Tool

Field Programmable Technology

T. Hussain, M. Pericas, N. Nacho, and E. Ayguade
Reconfigurable Memory Controller with Programmable Pattern Support

5th HiPEAC Workshop on Reconfigurable Computing (WRC 2011)

T. Hussain, M. Pericas, and E. Ayguade
A Template System for the Efficient Compilation of Domain Abstractions onto Reconfigurable Computers

5th HiPEAC Workshop on Reconfigurable Computing (WRC 2011)

M. Shafiq, M. Pericas, and E. Ayguade
TARCAD: A template architecture for reconfigurable accelerator designs

IEEE Symposium on Application Specific Processors (SASP)

M. Shafiq, M. Pericas, N. Navarro, and E. Ayguade
Integrating Dataflow Abstractions into Transactional Memory

First Workshop on Systems for Future Multi-Core Architectures (SFMA'11)

V. Gajinov, M. Milovanovic, O. Unsal, A. Cristal, E. Ayguade, and M. Valero
Assessing Accelerator-based HPC Reverse Time Migration

Transactions on Parallel and Distributed Systems, Special Issue on Accelerators

M. Araya-Polo, J. Cabezas, M. Hanzich, M. Pericas, E. Morancho, I. Gelado, M. Shafiq, F. Rubio, J M.. Cela, E. Ayguade, N. Navarro, and M. Valero

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