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2012

DMA++: On the Fly Data Realignment for On-Chip Memories

Computers, IEEE Transactions on

N. Vujic, F. Cabarcas, M. González, A. Ramirez, X. Martorell, and E. Ayguade
On the Simulation of Large-scale Architectures Using Multiple Application Abstraction Levels

ACM Transactions on Architecture and Code Optimization

A. Rico, F. Cabarcas, C. Villavieja, M. Pavlovic, A. Vega, Y. Etsion, A. Ramirez, and M. Valero

2011

Trace-driven simulation of multithreaded applications

2011 IEEE International Symposium on Performance Analysis of Systems and Software

A. Rico, A. Duran, F. Cabarcas, Y. Etsion, A. Ramirez, and M. Valero
Scalable multicore architectures for long DNA sequence comparison

Concurrency and Computation Practice and Experience

F. Sánchez, F. Cabarcas, A. Ramirez, and M. Valero

2010

The SARC Architecture

IEEE Micro

A. Ramirez, F. Cabarcas, B. Juurlink, M A. Mesa, F. Sánchez, A. Azevedo, C. Meenderinck, C. Ciobanu, S. Isaza, and G. N. Gaydadjiev
Long DNA Sequence Comparison on Multicore Architectures

16th international Euro-Par conference on Parallel processing

F. Sánchez, F. Cabarcas, A. Ramirez, and M. Valero
Comparing last-level cache designs for CMP architectures

IFMT '10: International Forum on Next-Generation Multicore/Manycore Technologies

A. Vega, A. Rico, F. Cabarcas, A. Ramirez, and M. Valero
Interleaving Granularity on High Bandwidth Memory Architecture for CMPs

Intl. Conf. on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS X)

F. Cabarcas, A. Rico, Y. Etsion, and A. Ramirez
Task Superscalar: An Out-of-Order Task Pipeline

IEEE/ACM Intl. Symp. on Microarchitecture (MICRO-43)

Y. Etsion, F. Cabarcas, A. Rico, A. Ramirez, R. M. Badia, E. Ayguade, J. Labarta, and M. Valero
DMA++: On the Fly Data Realignment for On-Chip Memories

16th IEEE International Symposium on High-Performance Computer Architecture

N. Vujic, M. González, E. Ayguade, X. Martorell, A. Ramirez, and F. Cabarcas

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