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2005

Software Trace Cache

IEEE Transactions on Computers

A. Ramirez, J. Lluis Larriba-Pey, and M. Valero

2004

A Low-Complexity Fetch Architecture for High-Performance Superscalar Processors

ACM Transactions on Architecture and Code Optimization

O. J. Santana, A. Ramirez, J. Lluis Larriba-Pey, and M. Valero
A Low Complexity Fetch Architecture for High Performance Superscalar Processors

ACM Transactions on Architecture and Compiler Optimizations (TACO)

M. Valero, O. J. Santana, A. Ramirez, and J. Lluis Larriba-Pey

2002

Software Trace Cache for Commercial Applications

International Journal of Parallel Programming

A. Ramirez, J. Lluis Larriba-Pey, C. Navarro, M. Valero, and J. Torrellas
Branch classification for SMT fetch gating

6th Workshop on Multithreaded Execution, Architecture and Compilation (MTEAC6)

P. Knijnenburg, A. Ramirez, J. Lluis Larriba-Pey, and M. Valero
Branch Classification to Control Instruction Fetch in Simultaneous Multithreaded Architectures

International Workshop on Innovative Architecture (IWIA 2002)

P. Knijnenburg, A. Ramirez, F. Latorre, J. Lluis Larriba-Pey, and M. Valero
Fetching Instruction Streams

35th Annual International Symposium on Microarchitecture (MICRO-35)

A. Ramirez, O. J. Santana, J. Lluis Larriba-Pey, and M. Valero

2001

Branch Prediction Using Profile Data

7th International Euro-Par Conference (Euro-Par'2001)

A. Ramirez, J. Lluis Larriba-Pey, and M. Valero
Code Layout Optimizations for Transaction Processing Workloads

28th Annual International Symposium on Computer Architecture (ISCA-28)

A. Ramirez, L. A. Barroso, K. Gharachorloo, R. Cohn, J. Lluis Larriba-Pey, G. Lowney, and M. Valero
Instruction Fetch Architectures and Code Layout Optimizations

Proceedings of the IEEE

A. Ramirez, J. Lluis Larriba-Pey, and M. Valero

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