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Mostrant 101 - 110 resultats de 224

2018

New High Performance Computing Software for Multiphysics Simulations of Fusion Reactors

Nuclear Engineering and Design

A. Gutierrez-Milla, M. J. Mantsinen, J. Abella, G. Houzeaux, C. Riera-Auge, and X. Sáez
Reconciling Time Predictability and Performance in Future Computing Systems

IEEE Design & Test

F. J. Cazorla, J. Abella, E. Mezzetti, C. Hernandez, T. Vardanegay, and G. Bernat

2017

Computing Safe Contention Bounds for Multicore Resources with Round-Robin and FIFO Arbitration

IEEE Transactions on Computers

G. Fernandez, J. Jalle, J. Abella, E. Quiñones, T. Vardanega, and F. J. Cazorla
Work-in-Progress Paper: An Analysis of the Impact of Dependencies on Probabilistic Timing Analysis and Task Scheduling

2017 IEEE Real-Time Systems Symposium (RTSS)

E. Mezzetti, J. Abella, C. Hernandez, and F. J. Cazorla
On the tailoring of CAST-32A certification guidance to real COTS multicore architectures

2017 12th IEEE International Symposium on Industrial Embedded Systems (SIES)

I. Agirre, J. Abella, M. Azkarate-Askasua, and F. J. Cazorla
Design and Implementation of a Time Predictable Processor: Evaluation With a Space Case Study

Euromicro Conference on Real-Time Systems

C. Hernández, J. Abella, F. J. Cazorla, A. Bardizbanyan, J. Andersson, F. Cros, and F. Wartel
Execution time distributions in embedded safety-critical systems using extreme value theory

International Journal of Data Analysis Techniques and Strategies

J. Del Castillo, M. Padilla, J. Abella, and F. J. Cazorla
Boosting Guaranteed Performance in Wormhole NoCs with Probabilistic Timing Analysis

2017 Euromicro Conference on Digital System Design (DSD)

M. Slijepcevic, C. Hernandez, J. Abella, and F. J. Cazorla
SEDEA: A Sensible Approach to Account DRAM Energy in Multicore Systems

2017 29th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD)2017 29th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD)

Q. Liu, M. Moreto, J. Abella, F. J. Cazorla, and M. Valero
Modelling bus contention during system early design stages

2017 12th IEEE International Symposium on Industrial Embedded Systems (SIES)

D. Trilla, C. Hernandez, J. Abella, and F. J. Cazorla

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