Description
Limited instruction level parallelism and the power wall motivated the design of chip multiprocessor (CMP) architectures. In CMP architectures, the transistors provided by the technology improvement are used to build multiple processing engines that can simultaneously execute several (numerous) software threads. CMP processors deliver superior performance (throughput) and higher performance-per-watt ratio than single-threaded architectures. Therefore, CMP architectures are the mainstream processor design used in large High Performance Computing (HPC) clusters. On the other hand, simultaneous execution of numerous software threads on a single chip increases the stress on the memory system. While CMP architectures effectively increase the computational performance of a chip, it is unclear whether currently-used memory systems can scale to supply future CMP processors with sufficient data.
Several studies have already shown that limitations of present memory systems, either by means of capacity or bandwidth, are likely to have a strong negative impact on the scalability of memory systems of future CMP architectures, and large-scale HPC clusters in particular. In this project, Samsung Electronics Co., Ltd. and BSC studied the memory system requirements of large HPC systems.
The overall objective of the project was to present findings that can be used to enhance the design of memory systems for state-of-the-art and future HPC clusters. In order to reach this objective, we performed a profound characterization of memory behavior and memory requirements of large-scale HPC applications. Also, we explored different features of high-end memory components and analyzed their suitability for HPC systems.