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Inici > Vector Processing-Aware Advanced Clock-Gating Techniques for Low-Power Fused Multiply-Add

Vector Processing-Aware Advanced Clock-Gating Techniques for Low-Power Fused Multiply-Add

URL:  http://ieeexplore.ieee.org/document/8252727/

Authors: Ratković, Ivan / Palomar, Oscar / Stanic, Milan / Unsal, Osman / Cristal, Adrian / Valero, Mateo

Publication: IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Pagination: 1 - 14

Barcelona Supercomputing Center - Centro Nacional de Supercomputación
Source URL (retrieved on 1 abr 2023 - 04:13): https://www.bsc.es/ca/research-and-development/publications/vector-processing-aware-advanced-clock-gating-techniques-low