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Inici > ShadowHTM: Using a dual-bitcell L1 Data Cache to Improve Hardware Transactional Memory Performance

ShadowHTM: Using a dual-bitcell L1 Data Cache to Improve Hardware Transactional Memory Performance

Authors: Armejach, Adrià / Seyedi, Azam / Gil, Rubén Titos / Hur, Ibrahim / Unsal, Osman / Cristal, Adrián / Valero, Mateo

Number: UPC-DAC-RR-2010-49

Barcelona Supercomputing Center - Centro Nacional de Supercomputación
Source URL (retrieved on 11 oct 2024 - 17:44): https://www.bsc.es/ca/research-and-development/publications/shadowhtm-using-dual-bitcell-l1-data-cache-improve-hardware