Verification engineer for an out-of-order processor and accelerators (RE1/RE2)

Job Reference



Verification engineer for an out-of-order processor and accelerators (RE1/RE2)

Data de tancament

Dijous, 30 Setembre, 2021
Reference: 173_21_CS_HPDA_RE2
Job title: Verification engineer for an out-of-order processor and accelerators (RE1/RE2)


About BSC
The Barcelona Supercomputing Center - Centro Nacional de Supercomputación (BSC-CNS) is the leading supercomputing center in Spain. It houses MareNostrum, one of the most powerful supercomputers in Europe, and is a hosting member of the PRACE European distributed supercomputing infrastructure. The mission of BSC is to research, develop and manage information technologies in order to facilitate scientific progress. BSC combines HPC service provision and R&D into both computer and computational science (life, earth and engineering sciences) under one roof, and currently has over 700 staff from 49 countries.

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Context And Mission
The eProcessor EuroHPC project combines open source software (SW)/hardware (HW) to deliver the first completely open source European full stack ecosystem based on a new RISC-V CPU, coupled to multiple diverse accelerators that target traditional HPC and extend into mixed precision workloads for High Performance Data Analytics (HPDA), (AI, ML, DL and Bioinformatics). eProcessor will be extendable (open source), energy-efficient (low power), extreme-scale (high performance), suitable for uses in HPC and embedded applications, and extensible (easy to add on-chip and/or off-chip components).

eProcessor combines cutting edge research utilizing SW/HW co-design to achieve sustained processor and system performance for (sparse and mixed-precision) HPC and HPDA workloads by combining a high performance low power (architecture and circuit techniques) out-of-order processor core with novel, adaptive on-chip memory structures and management, as well as fault tolerance features. These software-hardware co-design solutions span the full stack from applications to runtimes, tools, OS, and the CPU and accelerators. This can only be done with a combination of SW simulation, HW emulation using FPGAs, and real ASIC prototypes that demonstrate the full stack feasibility of the hardware and software, in a modern technology node that can easily be adopted for a near-future HPC implementation.

We are seeking one talented and motivated professional with expertise in modern Design Verification methodologies, targeting ASICs tapeouts.
Key Duties
  • You will use your design and verification expertise to verify complex digital designs.
  • You will collaborate closely with design and verification engineers in active projects and perform hands-on verification.
  • Using your UVM, SystemVerilog and problem-solving skills, you will build efficient and effective verification environments that exercise processor designs through their corner-cases and expose all types of bugs.
  • You will be responsible for the full life cycle of verification, from verification planning to test execution, to collecting and closing coverage.
  • Education
    • Bachelor’s or Master’s Degree in Electrical Engineering or Computer Engineering or equivalent level of professional experience.
  • Essential Knowledge and Professional Experience
    • Experienced with the full verification life cycle from test planning to sign-off.
    • Knowledge of and experience with industry-standard simulators (Model/QuestaSim, VCS, etc.), revision control systems and regression systems.
    • Experienced in all latest DV methodologies: UVM, SystemVerilog Assertions, functional coverage, Assembly/C-based random/constrained-random Verification, Formal Verification, Verification IPs.
    • Experienced in developing a DV plan based on Functional Specification, create and build the necessary verification test bench/infrastructure, develop tests and verify design.
    • Strong debugging skills and able to work with design engineers to deliver functionally correct design blocks.
    • Agile development and open source development, deployment, and support, including GitHub or equivalent.
    • Strong scripting experience using scripting languages like Python, Perl, or Tcl.
    • Plan the verification of complex digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
    • Identify and write all types of coverage measures for stimulus and corner-cases. Close coverage measures to identify verification holes and to show progress towards tape-out.
    • Familiarity with Linux.
    • Fluency in English is essential, Spanish is welcome.
  • Additional Knowledge and Professional Experience
    • Experience with top-level and processor-based SoC and DLP (GPU/SIMD/Vector) verification is a big plus.
    • Knowledge of out-of-order processor and accelerator architecture and design is a big plus.
  • Competences
    • The candidate must be an effective communicator, multitask, and work well on collaborative designs.
    • Keeps abreast of technology trends.
    • Ability to think creatively.
    • Ability to work independently and make decisions.
    • Ability to take initiative, prioritize and work under set deadlines and pressure.
  • The position will be located at BSC within the Computer Sciences Department
  • We offer a full-time contract, a good working environment, a highly stimulating environment with state-of-the-art infrastructure, flexible working hours, extensive training plan, tickets restaurant, private health insurance, fully support to the relocation procedures
  • Duration: Temporary - 1 year (renewal until the end of eProcessor, 3 years in total) renewable
  • Salary: we offer a competitive salary commensurate with the qualifications and experience of the candidate and according to the cost of living in Barcelona
  • Starting date: ASAP
Applications Procedure
All applications must include:

  • A Cover Letter with a statement of interest in English, including two contacts for further references - Applications without this document will not be considered

  • A full CV in English including contact details

The vacancy will remain open until suitable candidate has been hired. Applications will be regularly reviewed and potential candidates will be contacted.
Diversity and Equal Opportunity Employment
BSC-CNS is an equal opportunity employer committed to diversity and inclusion. We are pleased to consider all qualified applicants for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, age, disability or any other basis protected by applicable state or local law.
This position is reserved for candidates who meet the requirements and have the legal status of disabled persons with a degree of disability equal to or greater than 33%. In case there are no applicants with disabilities that meet the requirements, the rest of the candidates without declared disability will be evaluated.


Application Form

please choose one of this and if needed describe the option : - BSC Website - Euraxess - HiPeac - LinkedIn - Networking/Referral: include who and how - Events (Forum, career fairs): include who and how - Through University: include the university name - Specialized website (Metjobs, BIB, other): include which one - Other social Networks: (Twitter, Facebook, Instagram, Youtube): include which one - Other (Glassdoor, ResearchGate, job search website and other cases): include which one
Please, upload your CV document using the following name structure: Name_Surname_CV
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Please, upload your CV document using the following name structure: Name_Surname_CoverLetter
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Please, upload your CV document using the following name structure: Name_Surname_OtherDocument
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** Consider that the information provided in relation to gender and nationality will be used solely for statistical purposes.