Computer Architecture - Operating Systems (CAOS)

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Mostrant 241 - 270 resultats de 296

2010

Designing OS for HPC Applications: Scheduling

R. Gioiosa, S. A. McKee, and M. Valero
Portable, Scalable, per-Core Power Estimation for Intelligent Resource Management

B. Goel, S. A. McKee, R. Gioiosa, K. Singh, M. Bhadauria, and M. Cesati
J-DSE: Joint Software and Hardware Design Space Exploration for Application Specific Processors

M. Paolieri, I. Bonesana, R. Gioiosa, and M. Valero
MERASA: Multi-Core Execution of Hard Real-Time Applications Supporting Analysability

T. Ungerer, F. Cazorla, P. Sainrat, G. Bernat, Z. Petrov, H. Casse, C. Rochange, E. Quinones, S. Uhrig, M. Gerdes, I. Guliashvili, M. Houston, F. Kluge, and S. Met
Thread to Strand Binding of Parallel Network Applications in Massive Multi-Threaded Systems

P. Radojkovic, V. Cakarevic, J. Verdú, A. Pajuelo, F. Cazorla, M. Nemirovsky, and M. Valero
Adapting Cache Partitioning Algorithms to Real pseudo-LRU Replacement Policies

K. Kedzierski, M. Moreto, F. Cazorla, and M. Valero
FlexDCP: a QoS framework for CMP architectures

ACM Operating Systems Review, Special Issue on the Interaction among the OS, Compilers, and Multicore Processors

M. Moreto, F. Cazorla, A. Ramirez, R. Sakellariou, and M. Valero

2009

Thread to Core Assignment in SMT On-Chip Multiprocessors

21st International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD'09)

C. Acosta, F. Cazorla, A. Ramirez, and M. Valero
An Analyzable Memory Controller for Hard Real-Time CMPs

IEEE Embedded Systems Letters

M. Paolieri, E. Quinones, F. Cazorla, and M. Valero
pseudo-LRU based Cache Partitioning Algorithms

K. Kedzierski, M. Moreto, F. Cazorla, and M. Valero
CPU accounting in CMP Processors

C. Luque, M. Moreto, F. Cazorla, R. Gioiosa, A. Buyuktosunoglu, and M. Valero
FlexDCP: a QoS framework for CMP architectures

ACM SIGOPS Operating System Review, Special Issue on the Interaction among the OS, Compilers, and Multicore Processors

M. Moreto, F. Cazorla, A. Ramirez, R. Sakellariou, and M. Valero
Using Randomized Caches in Probabilistic Real-Time Systems

E. Quinones, E. D. Berger, G. Bernat, and F. Cazorla
Hardware Support for WCET Analysis of Multicore Systems

M. Paolieri, E. Quinones, F. Cazorla, G. Bernat, and M. Valero
ITCA: Inter-Task Conflict-Aware CPU Accounting for CMPs

C. Luque, M. Moreto, F. Cazorla, R. Gioiosa, A. Buyuktosunoglu, and M. Valero
Efficient Execution of Mixed Application Workloads in a Hard Real-Time

M. Paolieri, E. Quinones, F. Cazorla, and M. Valero
Characterizing the resource-sharing levels in the UltraSPARC T2 Processor

V. Cakarevic, P. Radojkovic, J. Verdú, A. Pajuelo, F. Cazorla, M. Nemirovsky, and M. Valero

2008

Dynamic Cache Partitioning Based on the MLP on Cache Misses.

Transactions on HiPEAC

M. Moreto, F. Cazorla, A. Ramirez, and M. Valero
MFLUSH: Handling Long-latency loads in SMT On-Chip Multiprocessors.

International Conference on Parallel Processing (ICPP)

C. Acosta, F. Cazorla, A. Ramirez, and M. Valero
Scheduling Real-Time Systems With Explicit Resource Allocation Processors

C. Boneti, F. Cazorla, R. Gioiosa, and M. Valero
Understanding the overhead of the spin-lock loop in CMT architectures

V. Cakarevic, P. Radojkovic, J. Verdú, A. Pajuelo, R. Gioiosa, F. Cazorla, M. Nemirovsky, and M. Valero
A two-level Load/Store Queue based on Execution Locality

M. Pericas, R. González, F. Cazorla, A. Cristal, A. Veidenbaum, D. A. Jiménez, and M. Valero
Selection of the Register File Size and the Resource Allocation Policy on SMT Processors

J. J. Alastruey, F. Cazorla, T. Monreal, V. Viñals, and M. Valero