Computer Architecture - Operating Systems (CAOS)

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Mostrant 181 - 210 resultats de 298

2013

On the Convergence of Mainstream and Mission Critical Markets

50th Annual Design Automation Conference (DAC)

S. Girbal, M. Moreto, A. Grasset, J. Abella, E. Quinones, F. Cazorla, and S. Yehia
Probabilistic Timing Analysis on Conventional Cache Designs

ACM/IEEE Design, Automation, and Test in Europe (DATE)

L. Kosmidis, C. Curtsinger, E. Quinones, J. Abella, E. D. Berger, and F. Cazorla
A Cache Design for Probabilistically Analysable Real-Time Systems

ACM/IEEE Design, Automation, and Test in Europe (DATE)

L. Kosmidis, J. Abella, E. Quinones, and F. Cazorla
Improving the Effective use of Multithreaded Architectures: Implications on Compilation, Thread Assignment, and Timing Analysis

P. Radojkovic
Per-task Energy Accounting in Computing Systems

In IEEE Computer Architecture Letters (CAL)

Q. Liu, V. Jimenez, M. Moreto, J. Abella, and F. Cazorla
Performance Analysis Techniques for the Exascale Co-Design Process

Proceedings of International Conference on Parallel Computing (PARCO)

M. Schulz, A. Bhatele, J. Belak, P. - T. Bremer, M. Casas, G. Bronevetsky, T. Gamblin, K. Isaacs, I. Laguna, J. Levine, V. Pascucci, D. Richards, and B. Rountree
Achieving Timing Composability with Probabilistic Timing Analysis

In IEEE International Symposium on Object-component-service-oriented Real-time distributed computing (ISORC)

L. Kosmidis, E. Quinones, J. Abella, T. Vardanega, and F. Cazorla
Fair CPU Time Accounting in CMP+SMT Processors

ACM Trans. Archit. Code Optim.

C. Luque, M. Moreto, F. Cazorla, and M. Valero
Addressing Link Degradation in NoC-Based ULSI Designs

Euro-Par 2012: Parallel Processing Workshops

C. Hernández, F. Silla, and J. Duato
PROARTIS: Probabilistically Analyzable Real-Time Systems

ACM Trans. Embed. Comput. Syst.

F. Cazorla, E. Quinones, T. Vardanega, L. Cucu, B. Triquet, G. Bernat, E. Berger, J. Abella, F. Wartel, M. Houston, L. Santinelli, L. Kosmidis, C. Lo, and D. Maxim
A Hard Real-time Capable Multi-core SMT Processor

ACM Trans. Embed. Comput. Syst.

M. Paolieri, J. Mische, S. Metzlaff, M. Gerdes, E. Quinones, S. Uhrig, T. Ungerer, and F. Cazorla
Timing Effects of DDR Memory Systems in Hard Real-time Multicore Architectures: Issues and Solutions

ACM Trans. Embed. Comput. Syst.

M. Paolieri, E. Quinones, and F. Cazorla
Thread Assignment of Multithreaded Network Applications in Multicore/Multithreaded Processors

IEEE Transactions on Parallel and Distributed Systems

P. Radojkovic, V. Cakarevic, J. Verdú, A. Pajuelo, F. Cazorla, M. Nemirovsky, and M. Valero
Silicon-aware Distributed Switch Architecture for On-chip Networks

J. Syst. Archit.

A. Roca, C. Hernández, J. Flich, F. Silla, and J. Duato
Efficient Cache Architectures for Reliable Hybrid Voltage Operation Using EDC Codes

Proceedings of the Conference on Design, Automation and Test in Europe

B. Maric, J. Abella, and M. Valero
Task Mapping in Rectangular Twisted Tori

Proceedings of the High Performance Computing Symposium

C. Camarero, E. Vallejo, C. Martinez, M. Moreto, and R. Beivide
A hardware evaluation of cache partitioning to improve utilization and energy-efficiency while preserving responsiveness

Proceedings of the 40th Annual International Symposium on Computer Architecture

H. Cook, M. Moreto, S. Bird, K. Dao, D. A. Patterson, and K. Asanović
Tessellation: refactoring the OS around explicit resource containers with continuous adaptation

Proceedings of the 50th Annual Design Automation Conference

J. A. Colmenares, G. Eads, S. Hofmeyr, S. Bird, M. Moreto, D. Chou, B. Gluzman, E. Roman, D. B. Bartolini, N. Mor, K. Asanović, and J. D. Kubiatowicz

2012

Assessing the suitability of the NGMP multi-core processor in the Space domain

International Conference on Embedded Software (EMSOFT)

M. Fernández, R. Gioiosa, E. Quinones, L. Fossati, M. Zulianello, and F. Cazorla
Evaluating the impact of tlb misses on future HPC systems

The 26th IEEE International Parallel and Distributed Processing Symposium (IPDPS 2012)

A. Morari, R. Gioiosa, R. W. Wisniewski, B. Rosenburg, T. Inglett, and M. Valero
ADAM: An Efficient Data Management Mechanism for Hybrid High and Ultra-Low Voltage Operation Caches

ACM/IEEE Great Lakes Symposium on VLSI

B. Maric, J. Abella, and M. Valero
CPU Accounting for Multicore Processors

IEEE Transactions on Computers

C. Luque, M. Moreto, F. Cazorla, R. Gioiosa, A. Buyuktosunoglu, and M. Valero
PROARTIS: Probabilistically Analysable Real-Time Systems

ACM Transactions on Embedded Computing Systems

F. Cazorla, E. Quinones, T. Vardanega, L. Cucu-Grosjean, B. Triquet, E. D. Berger, J. Abella, F. Wartel, M. Houston, L. Santinelli, L. Kosmidis, C. Lo, and D. Maxim
Thread Assignment of Multithreaded Network Applications in Multicore/Multithreaded Processors

IEEE Transactions on Parallel and Distributed Systems

P. Radojkovic, V. Cakarevic, J. Verdú, A. Pajuelo, F. Cazorla, M. Nemirovsky, and M. Valero
Characterizing Thread Placement in the IBM POWER7 Processor

IEEE International Symposium on Workload Characterization (IISWC-2013)

S. Manousopoulos, M. Moreto, R. Gioiosa, N. Koziris, and F. Cazorla
Making Data Prefetch Smarter: Adaptive Prefetching on POWER7

21st International Conference on Parallel Architectures and Compilation Techniques (PACT-2012)

V. Jiménez, R. Gioiosa, F. Cazorla, A. Buyuktosunoglu, P. Bose, and F. P. O'Connell
Measurement-Based Probabilistic Timing Analysis for Multi-path Programs

24th Euromicro Conference on Real-Time Systems (ECRTS 2012)

L. Cucu-Grosjean, L. Santinelli, M. Houston, C. Lo, T. Vardanega, L. Kosmidis, J. Abella, E. Mezzetti, E. Quinones, and F. Cazorla
Optimal Task Assignment in Multithreaded Processors: A Statistical Approach

17th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-2012)

P. Radojkovic, V. Cakarevic, M. Moreto, J. Verdú, A. Pajuelo, F. Cazorla, M. Nemirovsky, and M. Valero
On the Evaluation of the Impact of Shared Resources in Multithreaded COTS Processors in Time-Critical Environments

ACM Transactions on Architecture and Code Optimization

P. Radojkovic, S. Girbal, A. Grasset, E. Quinones, S. Yehia, and F. Cazorla
SMT Malleability in IBM POWER5 and POWER6 Processors

IEEE Transactions on Computers

A. Morari, C. Boneti, F. Cazorla, R. Gioiosa, C-Y. Cher, A. Buyuktosunoglu, P. Bose, and M. Valero

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