Computer Architecture - Operating Systems (CAOS)

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Mostrant 121 - 150 resultats de 295

2015

Analysis and RTL Correlation of Instruction Set Simulators for Automotive Microcontroller Robustness Verification

Design Automation Conference (DAC), 2015 52nd ACM/EDAC/IEEE

J. Espinosa, C. Hernández, J. Abella, D. De Andres, and J. Carlos Ruiz
Characterizing Fault Propagation in Safety-Critical Processor Designs

21st IEEE International On-Line Testing Symposium (IOLTS), Elia, Halkidiki, Greece

J. Espinosa, C. Hernández, and J. Abella
Towards Certification-aware Fault Injection Methodologies Using Virtual Prototypes

10th IEEE Forum on specification & Design Languages (FDL), Barcelona, Spain

J. Espinosa, D. De Andres, J. Carlos Ruiz, C. Hernández, and J. Abella
Randomized Caches Can Be Pretty Useful to Hard Real-Time Systems

LITES

E. Mezzetti, M. Ziccardi, T. Vardanega, J. Abella, E. Quinones, and F. Cazorla
PACO: Fast Average-Performance Estimation for Time-Randomized Caches

2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC)

S. Milutinovic, E. Quinones, J. Abella, and F. Cazorla
WCET Analysis Methods: Pitfalls and Challenges on their Trustworthiness

10th IEEE International Symposium on Industrial Embedded Systems (SIES)

J. Abella, C. Hernández, E. Quinones, F. Cazorla, P. Ryan Conmy, M. Azkarate-askasua, J. Perez, E. Mezzetti, and T. Vardanega
CAP: Communication-aware Allocation Algorithm for Real-Time Parallel Applications on Many-cores

18th Euromicro Conference on Digital System Design (DSD) Madeira, Portugal

M. Panic, E. Quinones, C. Hernández, J. Abella, and F. Cazorla
Enabling TDMA Arbitration in the Context of MBPTA

18th Euromicro Conference on Digital System Design (DSD) Madeira, Portugal

M. Panic, J. Abella, C. Hernández, E. Quinones, T. Ungerer, and F. Cazorla
IEC-61508 SIL 3-compliant Pseudo-Random Number Generators for Probabilistic Timing Analysis

18th Euromicro Conference on Digital System Design (DSD) Madeira, Portugal

I. Agirre, M. Azkarate-askasua, J. Perez, C. Hernández, J. Abella, T. Vardanega, and F. Cazorla
A safety concept for a railway mixed-criticality embedded system based on multicore partitioning

13th IEEE International Conference on Dependable, Autonomic and Secure Computing (DASC-2015)

I. Agirre, M. Azkarate-askasua, A. Larrucea, J. Perez, T. Vardanega, and F. Cazorla
EPC: Extended Path Coverage for Measurement-based Probabilistic Timing Analysis

IEEE Real-Time Systems Symposium (RTSS) San Antonio, Texas

M. Ziccardi, E. Mezzetti, T. Vardanega, J. Abella, and F. Cazorla
Increasing Confidence on Measurement-Based Contention Bounds for Real-Time Round-Robin Buses

Design Automation Conference (DAC) San Francisco, CA

G. Fernandez, J. Jalle, J. Abella, E. Quinones, T. Vardanega, and F. Cazorla
Resource Usage Templates and Signatures for COTS Multicore Processors

DAC '15 Proceedings of the 52nd Annual Design Automation Conference

G. Fernandez, J. Jalle, J. Abella, E. Quinones, T. Vardanega, and F. Cazorla
Extreme value theory in computer sciences: The case of embedded safety-critical systems

6th International Conference on Risk Analysis (ICRA)

J. Abella, J. del Castillo, F. Cazorla, and M. Padilla
Seeking Time-Composable Partitions of Tasks for COTS Multicore Processors

IEEE 18th International Symposium on Real-Time Distributed Computing, (ISORC)

G. Fernandez, J. Abella, E. Quinones, L. Fossati, M. Zulianello, T. Vardanega, and F. Cazorla
OpenMP and Timing Predictability: A Possible Union?

DATE '15 Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition

R. Vargas, E. Quinones, and A. Marongiu
Towards Making a LEON3 Multicore Compatible with Probabilistic Timing Analysis

20th Data Systems In Aerospace Conference (DASIA), Barcelona, Spain

C. Hernández, J. Abella, F. Cazorla, J. Andersson, and A. Gianarro
Introduction to Partial Time Composability for COTS Multicores

SAC '15 Proceedings of the 30th Annual ACM Symposium on Applied Computing

G. Fernandez, J. Abella, E. Quinones, L. Fossati, M. Zulianello, T. Vardanega, and F. Cazorla
Timing Analysis of an Avionics Case Study on Complex Hardware/Software Platforms

DATE '15 Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition

F. Wartel, L. Kosmidis, A. Gogonel, A. Baldovin, Z. Stephenson, B. Triquet, E. Quinones, C. Lo, E. Mezzetti, I. Broster, J. Abella, L. Cucu-Grosjean, T. Vardanega, and F. Cazorla
Speeding up Static Probabilistic Timing Analysis

Architecture of Computing Systems – ARCS 2015

S. Milutinovic, J. Abella, D. Hardy, E. Quinones, I. Puaut, and F. Cazorla
Increasing Multicore System Efficiency through Intelligent Bandwidth Shifting

International Symposium on High- Performance Computer Architecture (HPCA)

V. J. Jiménez, A. Buyuktosunoglu, P. Bose, F. O’Connell, F. Cazorla, and M. Valero

2014