Publications

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C
O. J. Santana, Falcón, A., Ramirez, A., and Valero, M., A Complexity-Effective Decoding Architecture Based on Instruction Streams, Workshop on Complexity-Effective Design (WCED). 2004.
C. Acosta, Falcón, A., Ramirez, A., and Valero, M., A Complexity-Effective Simultaneous Multithreading Architecture, 34th International Conference on Parallel Processing (ICPP 2005). 2005.
C. Acosta, Falcón, A., Ramirez, A., and Valero, M., Complexity-Effectiveness in Multithreading Architectures, In 2005 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-2005). L'Aquila (Italy), pp. 79-82, 2005.
O. J. Santana, Falcón, A., Fernández, E., Medina, P., Ramirez, A., and Valero, M., A Comprehensive Analysis of Indirect Branch Prediction, 4th International Symposium on High Performance Computing (ISHPC-4). Springer-Verlag, Kansai Science City (Japan), pp. 133-141, 2002.
E
A. Falcón, Ramirez, A., and Valero, M., Effective Instruction Prefetching via Fetch Prestaging, IPDPS05. IEEE-ACM 19th International Parallel and Distributed Processing Symposium. 2005.
L
A. Falcón, Santana, O. J., Ramirez, A., and Valero, M., A latency conscious SMT branch predictor architecture, International Journal of High Performance Computing and Networking (IJHPCN), vol. 2, no. 1. pp. 11-21, 2004.
A. Falcón, Ramirez, A., and Valero, M., A Low-Complexity, High-Performance Fetch Unit for Simultaneous Multithreading Processors, 10th International Conference on High Performance Computer Architecture (HPCA-10). Madrid (Spain), pp. 244-253, 2004.
P
A. Falcón, Stark, J., Ramirez, A., Lai, K., and Valero, M., Prophet/Critic Hybrid Branch Prediction, 31st Annual International Symposium on Computer Architecture (ISCA-31). pp. 250-262, 2004.
T
A. Falcón, Santana, O. J., Ramirez, A., and Valero, M., Tolerating branch predictor latency on SMT, 5th International Symposium on High Performance Computing (ISHPC-V). Tokio (Japan), pp. 86-98, 2003.