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Kernel Partitioning of Streaming Applications: A Statistical Approach to an NP-complete Problem . International Symposium on Microarchitecture (MICRO-45) (2012).
Multithreaded COTS Processors for Time-Critical Environments . Transactions on Architecture and Code Optimization (TACO) (2012).
Optimal Task Assignment in Multithreaded Processors: A Statistical Approach. Architectural Support for Programming Languages and Operating Systems (ASPLOS) (2012).
PROARTIS: Probabilistically Analysable Real-Time Systems. Transactions on Embedded Computing Systems (2012).
A Case for Energy-Aware Accounting and Billing in Large-Scale Computing Facilities Cost Metrics and Design Implications. IEEE Micro (2011).
Characterizing Power and Temperature Behavior of POWER6-Based System. (invited paper). IEEE Journal of Emerging and Selected Topics in Circuits and Systems (2011).
Exploiting Intra-Task Slack Time of Load Operations for DVFS in Hard Real-Time Multi-core Systems. In Work in Progess (WiP), under the the 24nd Euromicro Conference on Real-Time Systems (ECRTS 2011) (2011).
Hybrid High-Performance Low-Power and Ultra-Low Energy Reliable Caches. International Conference on Computing Frontiers (CF) 12:1-12:2 (2011).
IA3: An Interference Aware Allocation Algorithm for Multicore Hard Real-Time Systems. (2011).at <http://www.rtas.org/>
Online Performance Prediction in Processors with DVFS Capabilities. ACACES 2011. Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems (2011).
RVC: A Mechanism for Time-Analyzable Real-Time Processors with Faulty Caches. (2011).at <http://www.hipeac.net/conference>
RVC-based time-predictable faulty caches for safety-critical systems. IOLTS 25-30 (2011).at <http://dblp.uni-trier.de/db/conf/iolts/iolts2011.html#AbellaQCVS11>
A Software-Pipelined Approach to Multicore Execution of Timing Predictable Multi-Threaded Hard Real-Time Tasks. (2011).at <http://dream.eng.uci.edu/isorc2011/>
Towards improved survivability in safety-critical systems. International On-Line Testing Symposium (IOLTS) 240-245 (2011).
A Case for Energy Aware Accounting in Large Scale Computing Facilities: Cost Metrics and Implications for Processor Design. (2010).
FlexDCP: a QoS framework for CMP architectures. ACM Operating Systems Review, Special Issue on the Interaction among the OS, Compilers, and Multicore Processors 43, 86-96 (2010).
MERASA: Multi-Core Execution of Hard Real-Time Applications Supporting Analysability. (2010).at <http://www.computer.org/portal/web/micro/home>
On the Problem of Evaluating the Performance of Multiprogrammed Workloads. . IEEE Transactions on Computers 59, (2010).
Thread to Strand Binding of Parallel Network Applications in Massive Multi-Threaded Systems. (2010).
An Analyzable Memory Controller for Hard Real-Time CMPs. IEEE Embedded Systems Letters 1, (2009).
CPU accounting in CMP Processors. (2009).
FlexDCP: a QoS framework for CMP architectures. ACM SIGOPS Operating System Review, Special Issue on the Interaction among the OS, Compilers, and Multicore Processors 43, 0163-5980 (2009).
Thread to Core Assignment in SMT On-Chip Multiprocessors. 21st International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD'09) (2009).
Balancing HPC Applications Through Smart Allocation of Resources in MT Processors. (2008).at <http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4536293>
Dynamic Cache Partitioning Based on the MLP on Cache Misses. Transactions on HiPEAC 3, 1-21 (2008).
A Dynamic Scheduler for Balancing HPC Applications. (2008).at <http://portal.acm.org/citation.cfm?id=1413412>
MFLUSH: Handling Long-latency loads in SMT On-Chip Multiprocessors. International Conference on Parallel Processing (ICPP) 173-181 (2008).
MLP-aware dynamic cache partitioning. 2008 International Conference on High Performance Embedded Architectures & Compilers (HiPEAC 2008) 337-352 (2008).
Multicore Resource Management. IEEE Micro 28, 6-16 (2008).