Publications

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2011
Jimenez, V., Cazorla, F., Gioiosa, R., Kursun, E., Isci, C., Buyuktosunoglu, A., Bose, P. & Valero, M. A Case for Energy-Aware Accounting and Billing in Large-Scale Computing Facilities Cost Metrics and Design Implications. IEEE Micro (2011).
Jimenez, V., Cazorla, F., Gioiosa, R., Valero, M., Boneti, C., Kursun, E., Cher, C., Isci, C., Buyuktosunoglu, A. & Bose, P. Characterizing Power and Temperature Behavior of POWER6-Based System. (invited paper). IEEE Journal of Emerging and Selected Topics in Circuits and Systems (2011).
Quiñones, E., Abella, J., Cazorla, F. & Valero, M. Exploiting Intra-Task Slack Time of Load Operations for DVFS in Hard Real-Time Multi-core Systems. In Work in Progess (WiP), under the the 24nd Euromicro Conference on Real-Time Systems (ECRTS 2011) (2011).
Maric, B., Abella, J., Cazorla, F. & Valero, M. Hybrid High-Performance Low-Power and Ultra-Low Energy Reliable Caches. International Conference on Computing Frontiers (CF) 12:1-12:2 (2011).
Paolieri, M., Quiñones, E., Cazorla, F., Davis, R.I. & Valero, M. IA3: An Interference Aware Allocation Algorithm for Multicore Hard Real-Time Systems. (2011).at <http://www.rtas.org/>
Liu, Q., Moretó, M., Abella, J. & Cazorla, F. Online Performance Prediction in Processors with DVFS Capabilities. ACACES 2011. Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems (2011).
Morari, A., Gioiosa, R., Wisniewski, R., Cazorla, F. & Valero, M. A Quantitative Analysis of OS Noise. (2011).at <http://www.ipdps.org/>
Abella, J., Quiñones, E., Cazorla, F., Sazeides, Y. & Valero, M. RVC: A Mechanism for Time-Analyzable Real-Time Processors with Faulty Caches. (2011).at <http://www.hipeac.net/conference>
Abella, J., Quiñones, E., Cazorla, F., Valero, M. & Sazeides, Y. RVC-based time-predictable faulty caches for safety-critical systems. IOLTS 25-30 (2011).at <http://dblp.uni-trier.de/db/conf/iolts/iolts2011.html#AbellaQCVS11>
Paolieri, M., Quiñones, E., Wolf, J., Petrov, Z., Cazorla, F., Uhrig, S. & Ungerer, T. A Software-Pipelined Approach to Multicore Execution of Timing Predictable Multi-Threaded Hard Real-Time Tasks. (2011).at <http://dream.eng.uci.edu/isorc2011/>
Abella, J., Cazorla, F., Quiñones, E., Grasset, A., Yehia, S., Bonnot, P., Gizopoulos, D., Mariani, R. & Bernat, G. Towards improved survivability in safety-critical systems. International On-Line Testing Symposium (IOLTS) 240-245 (2011).
2010
Kedzierski, K., Moreto, M., Cazorla, F. & Valero, M. Adapting Cache Partitioning Algorithms to Real pseudo-LRU Replacement Policies. (2010).
Jiménez, V.J., Cazorla, F., Gioiosa, R., Kursun, E., Isci, C., Buyuktosunoglu, A. & Valero, M. A Case for Energy Aware Accounting in Large Scale Computing Facilities: Cost Metrics and Implications for Processor Design. (2010).
Moreto, M., Cazorla, F., Ramirez, A., Sakellariou, R. & Valero, M. FlexDCP: a QoS framework for CMP architectures. ACM Operating Systems Review, Special Issue on the Interaction among the OS, Compilers, and Multicore Processors 43, 86-96 (2010).
Moreto, M., Paolieri, M., Abella, J., Quiñones, E., Cazorla, F. & Valero, M. Hard Real-Time Capable Multicore Processors for Space Applications. (2010).
Luque, C., Moreto, M., Cazorla, F., Gioiosa, R. & Valero, M. ITCA: Inter-Task Conflict-Aware CPU Accounting for CMPs. (2010).
Moreto, M., Cazorla, F., Sakellariou, R. & Valero, M. Load Balancing Using Dynamic Cache Allocation. (2010).
Ungerer, T., Cazorla, F., Sainrat, P., Bernat, G., Petrov, Z., Casse, H., Rochange, C., Quiñones, E., Uhrig, S., Gerdes, M., Guliashvili, I., Houston, M., Kluge, F. & Met, S. MERASA: Multi-Core Execution of Hard Real-Time Applications Supporting Analysability. (2010).at <http://www.computer.org/portal/web/micro/home>
Kedzierski, K., Cazorla, F., Gioiosa, R., Buyuktosunoglu, A. & Valero, M. Power and Performance Aware Reconfigurable Cache for CMPs. (2010).
Jiménez, V.J., Boneti, C., Cazorla, F., Gioiosa, R., Kursun, E., Cher, C.-Y., Isci, C., Buyuktosunoglu, A., Bose, P. & Valero, M. Power and Thermal Characterization of POWER6 System. (2010).
Cazorla, F., Pajuelo, A., Santana, O.J., Fernandez, E. & Valero, M. On the Problem of Evaluating the Performance of Multiprogrammed Workloads. . IEEE Transactions on Computers 59, (2010).
Radojkovic, P., Cakarevic, V., Verdú, J., Pajuelo, A., Cazorla, F., Nemirovsky, M. & Valero, M. Thread to Strand Binding of Parallel Network Applications in Massive Multi-Threaded Systems. (2010).
Jiménez, V.J., Gioiosa, R., Kursun, E., Cazorla, F., Cher, C.-Y., Buyuktosunoglu, A., Bose, P. & Valero, M. Trends and techniques for energy efficient architectures. (2010).
Kosmidis, L., Quiñones, E., Abella, J., Cazorla, F., Bernat, G. & Berger, E.D. Use of randomized caches in hard real-time systems. (2010).
Boneti, C., Gioiosa, R., Cazorla, F. & Valero, M. Using hardware resource allocation to balance HPC applications, Parallel and Distributed Computing. (2010).
2009
Paolieri, M., Quiñones, E., Cazorla, F. & Valero, M. An Analyzable Memory Controller for Hard Real-Time CMPs. IEEE Embedded Systems Letters 1, (2009).
Cakarevic, V., Radojkovic, P., Verdú, J., Pajuelo, A., Cazorla, F., Nemirovsky, M. & Valero, M. Characterizing the resource-sharing levels in the UltraSPARC T2 Processor. (2009).
Luque, C., Moreto, M., Cazorla, F., Gioiosa, R., Buyuktosunoglu, A. & Valero, M. CPU accounting in CMP Processors. (2009).
Paolieri, M., Quiñones, E., Cazorla, F. & Valero, M. Efficient Execution of Mixed Application Workloads in a Hard Real-Time. (2009).
Moreto, M., Cazorla, F., Ramirez, A., Sakellariou, R. & Valero, M. FlexDCP: a QoS framework for CMP architectures. ACM SIGOPS Operating System Review, Special Issue on the Interaction among the OS, Compilers, and Multicore Processors 43, 0163-5980 (2009).
Paolieri, M., Quiñones, E., Cazorla, F., Bernat, G. & Valero, M. Hardware Support for WCET Analysis of Multicore Systems. (2009).
Luque, C., Moreto, M., Cazorla, F., Gioiosa, R., Buyuktosunoglu, A. & Valero, M. ITCA: Inter-Task Conflict-Aware CPU Accounting for CMPs. (2009).
Kedzierski, K., Moreto, M., Cazorla, F. & Valero, M. pseudo-LRU based Cache Partitioning Algorithms. (2009).
Acosta, C., Cazorla, F., Ramirez, A. & Valero, M. Thread to Core Assignment in SMT On-Chip Multiprocessors. 21st International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD'09) (2009).
Quiñones, E., Berger, E.D., Bernat, G. & Cazorla, F. Using Randomized Caches in Probabilistic Real-Time Systems. (2009).
2008
Castillo, P.A., Mora, A.M., Merelo, J.J., Laredo, J.L., Moreto, M., Cazorla, F., Valero, M. & McKee, S.A. Architecture performance prediction using evolutionary artificial neural networks. (2008).
Boneti, C., Cazorla, F., Gioiosa, R., Corbalán, J., Labarta, J. & Valero, M. Balancing HPC Applications Through Smart Allocation of Resources in MT Processors. (2008).at <http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4536293>
Moreto, M., Cazorla, F., Ramirez, A. & Valero, M. Dynamic Cache Partitioning Based on the MLP on Cache Misses. Transactions on HiPEAC 3, 1-21 (2008).
Boneti, C., Gioiosa, R., Cazorla, F. & Valero, M. A Dynamic Scheduler for Balancing HPC Applications. (2008).at <http://portal.acm.org/citation.cfm?id=1413412>
Castillo, P.A., Merelo, J.J., Moreto, M., Cazorla, F., Valero, M., Mora, A.M., Laredo, J.L. & McKee, S.A. Evolutionary system for prediction and optimization of hardware architecture performance. (2008).
Radojkovic, P., Cakarevic, V., Verdú, J., Pajuelo, A., Gioiosa, R., Cazorla, F., Nemirovsky, M. & Valero, M. Measuring Operating System Overhead on CMT Processors. (2008).
Acosta, C., Cazorla, F., Ramirez, A. & Valero, M. MFLUSH: Handling Long-latency loads in SMT On-Chip Multiprocessors. International Conference on Parallel Processing (ICPP) 173-181 (2008).
Moreto, M., Cazorla, F., Ramirez, A. & Valero, M. MLP-aware dynamic cache partitioning. 2008 International Conference on High Performance Embedded Architectures & Compilers (HiPEAC 2008) 337-352 (2008).
Nesbit, K.J., Moreto, M., Cazorla, F., Ramirez, A., Valero, M. & Smith, J.E. Multicore Resource Management. IEEE Micro 28, 6-16 (2008).
Boneti, C., Cazorla, F., Gioiosa, R. & Valero, M. Scheduling Real-Time Systems With Explicit Resource Allocation Processors. (2008).
Alastruey, J.J., Cazorla, F., Monreal, T., Viñals, V. & Valero, M. Selection of the Register File Size and the Resource Allocation Policy on SMT Processors. (2008).

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