Publications

Export 20 results:
Author Title [ Type(Desc)] Year
Filters: Author is Josep Lluis Larriba-Pey  [Clear All Filters]
International Conferences
P. Knijnenburg, Ramirez, A., Larriba-Pey, J. L., and Valero, M., Branch classification for SMT fetch gating, 6th Workshop on Multithreaded Execution, Architecture and Compilation (MTEAC6). Istambul (Turkey), 2002.
A. Ramirez, Larriba-Pey, J. L., and Valero, M., Branch Prediction Using Profile Data, 7th International Euro-Par Conference (Euro-Par'2001). Manchester (United Kingdom), pp. 386-393, 2001.
A. Ramirez, Barroso, L. A., Gharachorloo, K., Cohn, R., Larriba-Pey, J. L., Lowney, G., and Valero, M., Code Layout Optimizations for Transaction Processing Workloads, 28th Annual International Symposium on Computer Architecture (ISCA-28). Göteborg (Sweden), pp. 155-164, 2001.
A. Ramirez, Larriba-Pey, J. L., and Valero, M., The Effect of Code Reordering on Branch Prediction, International Conference on Parallel Architectures and Compilation Techniques (PACT 2000). pp. 189-198, 2000.
A. Ramirez, Santana, O. J., Larriba-Pey, J. L., and Valero, M., Fetching Instruction Streams, 35th Annual International Symposium on Microarchitecture (MICRO-35). Istambul (Turkey), pp. 371-382, 2002.
A. Ramirez, Larriba-Pey, J. L., Navarro, C., Serrano, X., Torrellas, J., and Valero, M., Optimization of Instruction Fetch for Decision Support Workloads, International Conference on Parallel Processing. pp. 238-245, 1999.
A. Ramirez, Larriba-Pey, J. L., Navarro, C., Serrano, X., Torrellas, J., and Valero, M., Optimizing Instruction Fetch for Decision Support Workloads, 2nd Workshop on Computer Architecture Evaluation using Commercial Workloads (CAECW-2). 1999.
C. Navarro, Ramirez, A., Larriba-Pey, J. L., and Valero, M., On the Performance of Fetch Engines Running DSS Workloads, 6th International Euro-Par Conference (EuroPar'2000). Springer-Verlag, pp. 591-595, 2000.
A. Ramirez, Larriba-Pey, J. L., Navarro, C., Torrellas, J., and Valero, M., Software Trace Cache, International Conference on Supercomputing (ICS'1999). pp. 119-126, 1999.
A. Ramirez, Larriba-Pey, J. L., Navarro, C., Serrano, X., Torrellas, J., and Valero, M., Trace Cache Redundancy, X Jornadas de Paralelismo. pp. 39-44, 1999.
A. Ramirez, Larriba-Pey, J. L., and Valero, M., Trace Cache Redundancy: Red & Blue Traces, Sixth International Symposium on High-Performance Computer Architecture (HPCA'2000). pp. 325-333, 2000.
Journal
A. Ramirez, Larriba-Pey, J. L., and Valero, M., Instruction Fetch Architectures and Code Layout Optimizations, Proceedings of the IEEE, vol. 89, no. 11. pp. 1588-1609, 2001.
M. Valero, Santana, O. J., Ramirez, A., and Larriba-Pey, J. L., A Low Complexity Fetch Architecture for High Performance Superscalar Processors, ACM Transactions on Architecture and Compiler Optimizations (TACO), vol. 1, no. 2. pp. 220-245, 2004.
O. J. Santana, Ramirez, A., Larriba-Pey, J. L., and Valero, M., A Low-Complexity Fetch Architecture for High-Performance Superscalar Processors, ACM Transactions on Architecture and Code Optimization, vol. 1, no. 2. pp. 220-245, 2004.
A. Ramirez, Larriba-Pey, J. L., and Valero, M., Software Trace Cache, IEEE Transactions on Computers, vol. 54, no. 1. pp. 22-35, 2005.
A. Ramirez, Larriba-Pey, J. L., Navarro, C., Valero, M., and Torrellas, J., Software Trace Cache for Commercial Applications, International Journal of Parallel Programming, vol. 30, no. 5. pp. 373-395, 2002.
A. Ramirez, Larriba-Pey, J. L., and Valero, M., A Stream Processor Front-end, IEEE Technical Committee on Computer Architecture Newsletter. pp. 10-13, 2000.
Workshops
P. Knijnenburg, Ramirez, A., Latorre, F., Larriba-Pey, J. L., and Valero, M., Branch Classification to Control Instruction Fetch in Simultaneous Multithreaded Architectures, International Workshop on Innovative Architecture (IWIA 2002). Kohala Coast, Hawaii (United States), pp. 67-76, 2002.
C. Navarro, Ramirez, A., Larriba-Pey, J. L., and Valero, M., Fetch Engines and Databases, 3rd Workshop on Computer Architecture Evaluation using Commercial Workloads (CAECW-3). 2000.
A. Ramirez, Larriba-Pey, J. L., and Valero, M., Semi-static Branch Prediction for Optimized Code Layouts, 3rd Workshop on Computer Architecture Evaluation using Commercial Workloads (CAECW-3). 2000.