Publications

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International Conferences
Knijnenburg, P., Ramirez, A., Larriba-Pey, J.L. & Valero, M. Branch classification for SMT fetch gating. 6th Workshop on Multithreaded Execution, Architecture and Compilation (MTEAC6) (2002).
Ramirez, A., Larriba-Pey, J.L. & Valero, M. Branch Prediction Using Profile Data. 7th International Euro-Par Conference (Euro-Par'2001) 386-393 (2001).
Ramirez, A., Barroso, L.A., Gharachorloo, K., Cohn, R., Larriba-Pey, J.L., Lowney, G. & Valero, M. Code Layout Optimizations for Transaction Processing Workloads. 28th Annual International Symposium on Computer Architecture (ISCA-28) 155-164 (2001).
Ramirez, A., Larriba-Pey, J.L. & Valero, M. The Effect of Code Reordering on Branch Prediction. International Conference on Parallel Architectures and Compilation Techniques (PACT 2000) 189-198 (2000).
Ramirez, A., Santana, O.J., Larriba-Pey, J.L. & Valero, M. Fetching Instruction Streams. 35th Annual International Symposium on Microarchitecture (MICRO-35) 371-382 (2002).
Ramirez, A., Larriba-Pey, J.L., Navarro, C., Serrano, X., Torrellas, J. & Valero, M. Optimization of Instruction Fetch for Decision Support Workloads. International Conference on Parallel Processing 238-245 (1999).
Ramirez, A., Larriba-Pey, J.L., Navarro, C., Serrano, X., Torrellas, J. & Valero, M. Optimizing Instruction Fetch for Decision Support Workloads. 2nd Workshop on Computer Architecture Evaluation using Commercial Workloads (CAECW-2) (1999).
Navarro, C., Ramirez, A., Larriba-Pey, J.L. & Valero, M. On the Performance of Fetch Engines Running DSS Workloads. 6th International Euro-Par Conference (EuroPar'2000) 591-595 (2000).
Ramirez, A., Larriba-Pey, J.L., Navarro, C., Torrellas, J. & Valero, M. Software Trace Cache. International Conference on Supercomputing (ICS'1999) 119-126 (1999).
Ramirez, A., Larriba-Pey, J.L., Navarro, C., Serrano, X., Torrellas, J. & Valero, M. Trace Cache Redundancy. X Jornadas de Paralelismo 39-44 (1999).
Ramirez, A., Larriba-Pey, J.L. & Valero, M. Trace Cache Redundancy: Red & Blue Traces. Sixth International Symposium on High-Performance Computer Architecture (HPCA'2000) 325-333 (2000).
Workshops
Knijnenburg, P., Ramirez, A., Latorre, F., Larriba-Pey, J.L. & Valero, M. Branch Classification to Control Instruction Fetch in Simultaneous Multithreaded Architectures. International Workshop on Innovative Architecture (IWIA 2002) 67-76 (2002).
Navarro, C., Ramirez, A., Larriba-Pey, J.L. & Valero, M. Fetch Engines and Databases. 3rd Workshop on Computer Architecture Evaluation using Commercial Workloads (CAECW-3) (2000).
Ramirez, A., Larriba-Pey, J.L. & Valero, M. Semi-static Branch Prediction for Optimized Code Layouts. 3rd Workshop on Computer Architecture Evaluation using Commercial Workloads (CAECW-3) (2000).