Publications

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Ramirez, A., Larriba-Pey, J.L. & Valero, M. The Effect of Code Reordering on Branch Prediction. International Conference on Parallel Architectures and Compilation Techniques (PACT 2000) 189-198 (2000).
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Navarro, C., Ramirez, A., Larriba-Pey, J.L. & Valero, M. Fetch Engines and Databases. 3rd Workshop on Computer Architecture Evaluation using Commercial Workloads (CAECW-3) (2000).
Ramirez, A., Santana, O.J., Larriba-Pey, J.L. & Valero, M. Fetching Instruction Streams. 35th Annual International Symposium on Microarchitecture (MICRO-35) 371-382 (2002).
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Ramirez, A., Larriba-Pey, J.L. & Valero, M. Semi-static Branch Prediction for Optimized Code Layouts. 3rd Workshop on Computer Architecture Evaluation using Commercial Workloads (CAECW-3) (2000).
Ramirez, A., Larriba-Pey, J.L. & Valero, M. Software Trace Cache. IEEE Transactions on Computers 54, 22-35 (2005).
Ramirez, A., Larriba-Pey, J.L., Navarro, C., Torrellas, J. & Valero, M. Software Trace Cache. International Conference on Supercomputing (ICS'1999) 119-126 (1999).
Ramirez, A., Larriba-Pey, J.L., Navarro, C., Valero, M. & Torrellas, J. Software Trace Cache for Commercial Applications. International Journal of Parallel Programming 30, 373-395 (2002).
Ramirez, A., Larriba-Pey, J.L. & Valero, M. A Stream Processor Front-end. IEEE Technical Committee on Computer Architecture Newsletter 10-13 (2000).
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Ramirez, A., Larriba-Pey, J.L., Navarro, C., Serrano, X., Torrellas, J. & Valero, M. Trace Cache Redundancy. X Jornadas de Paralelismo 39-44 (1999).
Ramirez, A., Larriba-Pey, J.L. & Valero, M. Trace Cache Redundancy: Red & Blue Traces. Sixth International Symposium on High-Performance Computer Architecture (HPCA'2000) 325-333 (2000).