Publications

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2005
Ramirez, A., Larriba-Pey, J.L. & Valero, M. Software Trace Cache. IEEE Transactions on Computers 54, 22-35 (2005).
2000
Ramirez, A., Larriba-Pey, J.L. & Valero, M. The Effect of Code Reordering on Branch Prediction. International Conference on Parallel Architectures and Compilation Techniques (PACT 2000) 189-198 (2000).
Navarro, C., Ramirez, A., Larriba-Pey, J.L. & Valero, M. Fetch Engines and Databases. 3rd Workshop on Computer Architecture Evaluation using Commercial Workloads (CAECW-3) (2000).
Navarro, C., Ramirez, A., Larriba-Pey, J.L. & Valero, M. On the Performance of Fetch Engines Running DSS Workloads. 6th International Euro-Par Conference (EuroPar'2000) 591-595 (2000).
Ramirez, A., Larriba-Pey, J.L. & Valero, M. Semi-static Branch Prediction for Optimized Code Layouts. 3rd Workshop on Computer Architecture Evaluation using Commercial Workloads (CAECW-3) (2000).
Ramirez, A., Larriba-Pey, J.L. & Valero, M. A Stream Processor Front-end. IEEE Technical Committee on Computer Architecture Newsletter 10-13 (2000).
Ramirez, A., Larriba-Pey, J.L. & Valero, M. Trace Cache Redundancy: Red & Blue Traces. Sixth International Symposium on High-Performance Computer Architecture (HPCA'2000) 325-333 (2000).