Publications

Journals

Miquel Moretó, Francisco J. Cazorla, Alex Ramirez, Rizos Sakellariou and Mateo Valero. FlexDCP: a QoS framework for CMP architectures. ACM Operating Systems Review, pp. 86-96, vol. 43, no. 2. Special Issue on the Interaction among the OS, Compilers, and Multicore Processors, . .  , April 2010.



Cor Meenderinck, Arnaldo Azevedo, Ben Juurlink, Mauricio Álvarez and Alex Ramirez. Parallel Scalability of Video Decoders . Journal of Signal Processing Systems, pp. 173-194, vol. 57, no. 2,
, November 2009.



Arnaldo Azevedo, Cor Meenderinck, Ben Juurlink, Andrei Tereckho, Jan Hoogerbrugge, Mauricio Álvarez, Alex Ramirez and Mateo Valero. A Highly Scalable Parallel Implementation of H.264. Transactions on High-Performance Embedded Architectures and Compilers, vol. 4, no. 2, , September 2009.



Mauricio Álvarez, Alex Ramirez, Mateo Valero, Arnaldo Azevedo, Cor Meenderinck and Ben Juurlink. Performance Evaluation of Macroblock-level Parallelization of H.264 Decoding on a cc-NUMA Multiprocessor Architecture. Avances en Sistemas e Informática, pp. 219-228, vol. 6, no. 1, , June 2009.



Oliverio J. Santana, Ayose Falcón, Alex Ramirez and Mateo Valero. DIA: A Complexity-Effective Decoding Architecture. IEEE Transactions on Computers, pp. 448-462, vol. 58, no. 4., , April 2009.



Alejandro Rico, Alex Ramirez and Mateo Valero. Available task-level parallelism on the Cell BE. Scientific Programming, pp. 59-76, vol. 17, no. 1-2,
, February 2009.



Pieter Bellens, Josep M. Pérez, Felipe Cabarcas, Alex Ramirez, Rosa M. Badia and Jesús Labarta. CellSs: Scheduling techniques to better exploit memory hierarchy. Scientific Programming, pp. 77-95, vol. 17, no. 1-2,
, January 2009.



Kyle J. Nesbit, Miquel Moreto, Francisco J. Cazorla, Alex Ramirez, Mateo Valero, and Jim E. Smith . Virtual Private Machines: Hardware/Software Interactions in the Multicore Era. IEEE Micro, special issue on Interaction of Computer Architecture and Operating System in the Manycore Era, vol. 38, no. 3, , June 2008.



Miloš Milovanović, Roger Ferrer, Vladimir Gajinov, Osman S. Unsal, Adrian Cristal, Eduard Ayguadé and Mateo Valero. Nebelung: Execution Environment for Transactional OpenMP. International Journal of Parallel Programming. Vol 36, number 3, , May 2008.



Kyle J. Nesbit, Miquel Moretó, Francisco J. Cazorla, Alex Ramirez, Mateo Valero and James E. Smith. Multicore Resource Management. IEEE Micro, pp. 6-16, vol. 28, no. 3. Special issue on Interaction of Computer Architecture and Operating Systems., , May 2008.



Miquel Moreto, Francisco J. Cazorla, Alex Ramirez and Mateo Valero. Dynamic Cache Partitioning based on the MLP of Cache Misses. Transactions on High Performance Embedded Architectures and Compilers. vol. 3, no. 1, , March 2008.



Oliverio J. Santana, Alex Ramirez and Mateo Valero. Enlarging Instruction Streams. IEEE Transactions on Computers, vol. 56(10), , October 2007.



Tim Harris, Adrian Cristal, Osman S. Unsal, Eduard Ayguade, Fabrizio Gagliardi, Burton Smith, Mateo Valero. Transactional Memory: An Overview. IEEE Micro, vol 27 num 3, , April 2007.



Miquel Moretó, Francisco J. Cazorla, Alex Ramirez and Mateo Valero . Explaining Dynamic Cache Partitioning Speed Ups. IEEE Computer Architecture Letters, vol. 6, no. 1, , March 2007.



Koen de Bosschere, Wayne Luk, Xavier Martorell, Nacho Navarro, Mike O'Boyle, Dionisios Pnevmatikatos, Alex Ramirez, Pascal Saintrat, Andre Seznec, Per Stenstrom, Olivier Temam. High Performance Embedded Architectures and Compilation Roadmap. ransactions on HiPEAC Vol 1, Lecture Notes in Computer Science 4050, , January 2007.



F. Cazorla, P. M.W. Knijnenburg, R. Sakellariou, E. Fernandez, A. Ramirez and M. Valero. Predictable Performance in SMT processors: Synergy Between the OS and SMTs. IEEE Transactions on Computers, vol. 55(7) IEEE Computer Society 785-799, July 2006.


T. Morad, U. Weiser, A. Kolodny, M. Valero and E. Ayguadé . Performance, Power Efficiency and Scalability of Asymmetric Cluster Chip Multiprocessors. IEEE CAL, Computer Architecture Letters, Volume 5, number 1, pp.14-17 , June 2006.



J. Vidal, M. March, Ll. Cerdá, J. Corbal and M. Valero. A DRAM/SRAM Memory Scheme for Fast Packet Buffers. IEEE Transactions on Computers, Vol. 55 No. 5, pp. 588-602 , May 2006.



C. Alvarez, Jesus Corbal and M. Valero. Fuzzy Memoization for Floating Point Multimedia Applications. IEEE Transactions on Computers, Vol. 54, No 7, pp. 922-927 , July 2005.



A. Pajuelo, A. González and M. Valero. Speculative Execution for Hiding Memory Latency. Computer Architecture News, Vol. 33, No. 3. Special Issue: MEDEA 2004 Workshop, pp. 49-56 , June 2005.



E. Salami and M. Valero. Dynamic Memory Interval Test vs. Interprocedural Pointer Analiysis in Multimedia Applications. ACM Transactions on Architecture and Code Optimization, TACO Journal, Issue 2, pp. 199-219. , June 2005.



A. Cristal, O.Santana, F. Cazorla, M. Galluzzi, T. Ramírez and M. Valero. Kilo-instruction Processors: Overcoming the Memory Wall. IEEE-Micro Journal, Special Issue May/Jun05 Future trends of microprocessors , June 2005.



M. Pericás, R. González, A. Cristal, A. Veidenbaum and M. Valero. An Optimized Front-End Physical Register File with Banking and Writeback Filtering. Lectures Notes on Computer Science, 3471,

, January 2005.
Power Aware Computer Systems pp. 1-14, 2005


Ayose Falcón, Jared Stark, Alex Ramirez, Konrad Lai, and Mateo Valero. Better branch prediction through prophet/critic hybrids. IEEE Micro Journal, vol. 25(1), pp. 80-89, January 2005.



Alex Ramirez, Josep L. Larriba-Pey, Mateo Valero. Software Trace Cache. IEEE Transactions on Computers, vol. 54(1), pp. 22-35, January 2005.


T. Monreal, V. Viñals, A. González and M. Valero. Hardware Support for Early Register Release. IJHPCN. International Journal on High Performance and Networking, Vol. 3, No. 2/3, pp. 83-94 , January 2005.



M. Pericas, E. Ayguade, J. Zalamea, J. Llosa and M. Valero . Power and Performace Evaluation of Widened and Clustered VLIW Cores. LNCS, (to be published) , January 2005.



A. Cristal, O. Santana, J. Martínez and M. Valero. Towards Kilo-instruction Processors. ACM Transactions on Architecture and Code Optimization, TACO Journal, Vol. 1, No. 4, December 2004.



J. Zalamea, J. Llosa, E. Ayguadé and M. Valero . Software and Hardware Techniques to Optimize Register File Utilization in VLIW. International Journal of Parallel Programming, Vol 32, No 6, pp. 447-474 , December 2004.



M. Pericas, E. Ayguade, J. Zalamea, J. Llosa and M. Valero. Performance and Power Evaluation of Clustered VLIW Processors with Functional Units. Lecture Notes on Computer Science,
, November 2004.
Editor Springer-Verlag, Volume 3133


E. Salami and M. Valero. Initial Evaluation of Multimedia Extensions on VLIW Architectures. Lectures Notes on Computer Science. Editor Springer-Verlag, Volume 3133, November 2004.



T. Monreal, V. Viñals, J, González, A. González, M. Valero . Late Allocation and Early Release of Physical Registers. IEEE Transactions on Computers, Vol. 53, No 10, pp. 1244-1259 , October 2004.



Francisco J. Cazorla, Alex Ramirez, Mateo Valero, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández. QoS for High-Performance SMT Processors in Embedded Systems. IEEE Micro, vol. 24(4), pp. 24-31, July 2004.


Oliverio J. Santana, Alex Ramirez, Josep Lluis Larriba-Pey y Mateo Valero. A Low Complexity Fetch Architecture for High Performance Superscalar Processors. ACM Transactions on Architecture and Compiler Optimizations (TACO), pp. 220-245, June 2004.


O. J. Santana, A. Ramirez, J. L. Larriba-Pey, and M. Valero. A Low-Complexity Fetch Architecture for High-Performance Superscalar Processors. ACM Transactions on Architecture and Code Optimization, TACO Journal. vol 1, no. 2, pp 220-245. , June 2004.



J. Zalamea, J. Llosa, E. Ayguadé and M. Valero. Register-constrained Modulo Scheduling. IEEE Transactions on Parallel and Distributed Systems, vol. 15, no. 6, June 2004.



D.Ortega, M. Valero and E. AyguadéMay 2004. Dynamic Memory Instruction Bypassing. IJPP, International Journal on Parallel Processing . Plenun Published Corporation. Special issue on selected papers from ICS-2003, Vol 32(3), pp.199-224 , May 2004.



Francisco J. Cazorla, Enrique Fernandez, Alex Ramirez and Mateo Valero. Optimizing Long-Latency-Load-Aware Fetch Policies for SMT Processors. International Journal of High Performance Computing and Networking (IJHPCN), issue 2, Inderscience publishers, April 2004.


Ayose Falcon, Oliverio J. Santana, Alex Ramirez, Mateo Valero. A latency conscious SMT branch predictor architecture. International Journal of High Performance Computing and Networking (IJHPCN), issue 2, Inderscience publishers, April 2004.


A. Cristal, D. Ortega, J. Llosa and M. Valero. Future ILP Processors. IJHPCN. International Journal of High Performance Computing and Networking, Vol. 2, No 1, pp. 1-11 , January 2004.



M. A. Ramírez, A. Cristal, A. V. Veidenbaum, L. Villa and M. Valero Vol. I, N. 4, pp 153-161.. A Partitioned Instruction Queue to Reduce Instruction Wakeup Energy. IJHPCN. International Journal of High Performance Computing and Networking, Vol. I, N.4, pp 153-161
, January 2004.



M. Pericas, E. Ayguade, J. Zalamea, J. Llosa and M. Valero. High Performance and Low Power VLIW for Numerical Applications. IJHPCN. International Journal of High Performance Computing and Networking, To be published , January 2004.



Alex Ramirez, Josep-L. Larriba-Pey, Carlos Navarro, Mateo Valero and Josep Torrellas. Software Trace Cache for Commercial Applications. International Journal of Parallel Programming. pp. 373-395, vol. 30, no. 5,
, October 2002.



Alex Ramirez, Josep-L. Larriba-Pey and Mateo Valero. Instruction Fetch Architectures and Code Layout Optimizations. Proceedings of the IEEE, , November 2001.



Book chapters

Carlos Boneti, Francisco J. Cazorla, Roberto Gioiosa and Mateo Valero. Scheduling Real-Time Systems With Explicit Resource Allocation Processors . Dresden, Germany, Lecture Notes in Computer Science. Volume 4934/2008 , February 2008.
International Conference on Architecture of Computing Systems (ARCS)


Nehir Sonmez, Christian Perfumo, Srdjan Stipic, Adrian Cristal, Osman S. Unsal, Mateo Valero. Increasing the Performance of Haskell Software Transactional Memory. Trends in Functional Programming, Volume 8, , April 2007.



International Conferences

Mauricio Álvarez, Alex Ramirez, Mateo Valero, Arnaldo Azevedo, Cor Meenderinck and Ben Juurlink. Performance Evaluation of Macroblock-level Parallelization of H.264 Decoding on a cc-NUMA Multiprocessor Architecture. In 4CCC. 4th Colombian Computing Conference, Bucaramanga (Colombia),
, April 2010.



Nikola Vujic, Marc González, Eduard Ayguadé, Xavier Martorell, Alex Ramirez and Felipe Cabarcas. DMA++: On the Fly Data Realignment for On-Chip Memories. In 16th IEEE International Symposium on High-Performance Computer Architecture, Bangalore (India),

, January 2010.



Paul Carpenter, Alex Ramirez and Eduard Ayguadé. Buffer sizing for self-timed stream programs on heterogeneous distributed memory multiprocessors. In International conference on High-Performance Embedded Architectures and Compilers (HiPEAC) 2010), Pisa (Italy),
, January 2010.



Mauricio Álvarez, Alex Ramirez, Cor Meenderinck, Ben Juurlink and Mateo Valero. Scalability of Macroblock-level parallelism for H.264 decoding. In The Fifteenth International Conference on Parallel and Distributed Systems (ICPADS'09), Shenzhen (China),
, December 2009.



Paul Carpenter, Alex Ramirez and Eduard Ayguadé. Mapping stream programs onto heterogeneous multiprocessor systems. In International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES 2009), pp. 57-66, Grenoble (France), .  , October 2009.



Carmelo Acosta, Francisco J. Cazorla, Alex Ramirez and Mateo Valero. Thread to Core Assignment in SMT On-Chip Multiprocessors. In 21st International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD'09), Sao Pau,
, October 2009.



Paul Carpenter, Alex Ramirez and Eduard Ayguadé. The Abstract Streaming Machine: Compile-Time Performance Modelling of Stream Programs on Heterogeneous Multiprocessors. In IX International Workshop on Systems, Architectures, Modeling, and Simulation (SAMOS Workshop IX), pp. 12-23, Samos (Greece),
, July 2009.



Friman Sánchez, Alex Ramirez and Mateo Valero. Quantitative analysis of sequence alignment applications on multiprocessor architectures. In 6th ACM conference on Computing frontiers , pp. 61-70, Ischia (Italy),

, May 2009.



Friman Sánchez, Alex Ramirez and Mateo Valero. Exploiting Different Levels of Parallelism in the Biological Sequence Comparison Problem. In 4CCC. 4th Colombian Computing Conference, Bucaramanga (Colombia),


, April 2009.



Chinmay Kulkarni, Osman Unsal, Adrian Cristal, Eduard Ayguade and Mateo Valero. Turbocharging boosted transactions or: How I Learnt to Stop Worrying and Love Longer Transactions. 14th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP), , February 2009.



Ferad Zyulkyarov , Vladimir Gajinov, Osman Unsal , Adrian Cristal , Eduard Ayguade, Tim Harris , Mateo Valero. Atomic Quake: Use Case of Transactional Memory in an Interactive Multiplayer Game Server. 14th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP), , February 2009.



Arnaldo Azevedo, Cor Meenderinck, Ben Juurlink, Andrei Terechko, Jan Hoogerbrugge, Mauricio Alvarez, Alex Ramirez, Mateo Valero. Parallel H.264 Decoding on an Embedded Multicore Processor. 4th International Conference on High-Performance Embedded Architectures and Compilers (HiPEAC'09), , January 2009.



Carlos Boneti, Roberto Gioiosa, Francisco J. Cazorla and Mateo Valero. A Dynamic Scheduler for Balancing HPC Applications . Austin, USA, , November 2008.
In International Conference for High Performance Computing, Networking, Storage and Analysis (SC)


Isidro González, Marco Galluzzi, Alexander Veidenbaum, Alex Ramirez, Adrian Cristal and Mateo Valero. A distributed processor state management architecture for large-window processors. In 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41), pp. 11-22, Lake Como (Italy),

, November 2008.



C. Acosta, F.J.Cazorla, A. Ramírez and M. Valero. MFLUSH: Handling Long-latency loads in SMT On-Chip Multiprocessors. 37th International Conference on Parallel Processing (ICPP 2008), pp. 173 - 181. Portland, USA . ISBN 978-0-7695-3374-2 , September 2008.



Sebastian Isaza, Friman Sánchez, Georgi Gaydadjiev, Alex Ramirezi, Mateo Valero. Preliminary Analysis of the Cell BE Processor Limitations for Sequence Alignment Applications. mbedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS'08), , July 2008.



Carlos Boneti, Francisco J. Cazorla, Roberto Gioiosa, Chen-Yong Cher, Alper Buyuktosunoglu and Mateo Valero. Software-Controlled Priority Characterization of POWER5 Processor . Beijing, China, , June 2008.
International Symposium on Computer Architecture


Pedro A. Castillo, Juan Julian Merelo, Miquel Moreto, Francisco J. Cazorla, Mateo Valero, Antonio M. Mora, Juan Luis J. Laredo and Sally A. McKee. Evolutionary system for prediction and optimization of hardware architecture performance. IEEE Congress on Evolutionary Computation (CEC). Hong Kong, , June 2008.



Cristian Perfumo, Nehir Sonmez, Srdjan Stipic, Osman Unsal, Adrian Cristal, Tim Harris, Mateo Valero. The Limits of Software Transactional Memory (STM): Dissecting Haskell STM Applications on a Many-Core Environment. ACM International Conference on Computing Frontiers, , May 2008.



Arnaldo Azevedo, Cor Meenderinck, Ben Juurlink, Mauricio Alvarez, Alex Ramirez. Analysis of Video Filtering on the Cell Processor. 2008 IEEE International Symposium on Circuits and Systems (ISCAS'08), , May 2008.



Carlos Boneti, Francisco J. Cazorla, Roberto Gioiosa, Julita Corbalan, Jesus Labarta and Mateo Valero. Balancing HPC Applications Through Smart Allocation of Resources in MT Processors . Miami, Florida, USA, , April 2008.
International Parallel & Distributed Processing Symposium (IPDPS)


Miquel Moreto, Francisco J. Cazorla, Alex Ramirez and Mateo Valero. MLP-aware dynamic cache partitioning. International Conference on High Performance Embedded Architectures & Compilers, , January 2008.



Harald Servat, Xavier Aguilar, Cecilia Gonzalez, Daniel Cabrera, Daniel Jimenez. Drug Design Issues on the Cell BE. 3rd International Conference on High-Performance Embedded Architectures and Compilers (HiPEAC'08), , January 2008.



M. Moretó, F. J. Cazorla, A. Ramirez and M. Valero. MLP-aware dynamic cache partitioning. International Conference on Parallel Architectures and Compilation Techniques (PACT). Brasov, Romania, Poster Abstracts , September 2007.



Javier Vera Francisco J. Cazorla Alex Pajuelo Oliverio J. Santana Enrique Fernandez Mateo Valero . FAME: FAirly MEasuring Multithreaded Architectures . Brasov, Romania, , September 2007.
Parallel Architectures and Compilation Techniques (PACT)


Mauricio Alvarez, Esther Salami, Alex Ramirez, Mateo Valero. HD-VideoBench. A Benchmark for Evaluating High Definition Digital Video Applications. 2007 IEEE International Symposium on Workload Characterization (IISWC-2007), , September 2007.



Miquel Moreto, Francisco J. Cazorla, Alex Ramirez and Mateo Valero. Online Prediction of Applications Cache Utility. International Symposium on Systems, Architectures, MOdeling and Simulation (SAMOS), , July 2007.



Francisco J. Cazorla, Peter M.W. Knijnenburg, Rizos Sakellariou, Enrique Fernandez and Alex Ramirez Mateo Valero. On the Problem of Minimizing Workload Execution Time in SMT Processors . Samos, Greece, , July 2007.
IEEE International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (IC-SAMOS )


Paul Carpenter, David Rodenas, Xavier Martorell, Alex Ramirez and Eduard Ayguadé. A streaming machine description and programming model. In VII International Workshop on Systems, Architectures, Modeling, and Simulation (SAMOS 2007),
, July 2007.



M. Alvarez, E. Salami, J. labarta and M. Valero . April 25-27, 2007.. Performance Impact of Unaligned memory Operations in SIMD Extensions for Video CODEC Applications. ISPASS 2007. IEEE International Symposium on Performance Analysis of Systems and Software San José, California, USA.,
, April 2007.



Daniel Jimenez-Gonzalez, Xavier Martorell, Alex Ramirez. Performance Analysis of Cell Broadband Engine for High Memory Bandwidth Applications. IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS-2007), , April 2007.



Cristian Perfumo, Nehir Sonmez, Srdjan Stipic, Osman S. Unsal, Adrian Cristal, Mateo Valero. UnreadTVar: Extending Haskell Software Transactional Memory for Performance. The Eighth Symposium on Trends in Functional Programming, , April 2007.



Javier Vera, Francisco J. Cazorla, Alex Pajuelo, Oliverio J. Santana, Enrique Fernandez and Mateo Valero. Measuring the Performance of Multithreaded Processors . Austin, USA, Schaeffer Award to the technical quality of the paper , January 2007.
SPEC Benchmark Workshop (in conjunction with the Annual Meeting of the Standard Performance Evaluation Corporation (SPEC)


F. Sánchez, E. Salami, A. Ramírez and M.Valero. Performance Analysis of Sequence Alignment Applications. IISWC, IEEE Internacional Symposium on Workload Characterization, San José, USA , October 2006.



B. Slamat, D. Nicolaescu, A. Veidenbaum and M. Valero. Fast Speculative Address generation and Way Caching for Reducing L1 data Cache Energy. IEEE ICCD Internation Conference on Computer Design, San Francisco, USA , October 2006.



O. Santana, A. Falcón, A. Ramírez and M. Valero. Branch Predictor Guided Instruction Decoding. IEEE PACT Parallel Architectures and Compiler Techniques, Seatle , September 2006.



K. Kedziersky, F.J. Cazorla and M. Valero . Analysis of Simultaneous Multithreading Implementations in Current High-Performance Processors. ACACES 2006, Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems, Láquila, pp. 113-116. Academia Press, ISBN 90 382 0981 9 , July 2006.



M. Pericás, A. Cristal, R. González, F.J. Cazorla, D.A. Jiménez and M. Valero. Boosting ILP&TLP with the Flexible Multi-Core (FMC). Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems, ACACES 2006. Láquila pp. 125-128. Academia Press, ISBN 90 382 0981 9 , July 2006.



E. Vallejo, M. Galluzzi, A. Cristal, F. Vallejo, R. Beivide, P. Stenström, J.E. Smith and M. Valero. Chip Multiprocessors with Implicit Transactions. ACACES 2006, Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems, Láquila, pp. 167-170. Academia Press, ISBN 90 382 0981 9 , July 2006.



I. González, O. J. Santana, A. Pajuelo and M. Valero . . A First Glance at the Implementation of Precise Recoveries in Out-of-order Commit Processors. ACACES 2006, Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems, Láquila, pp. 9-11. Academia Press, ISBN 90 382 0981 9 , July 2006.



J. Alastruey, T. Monreal, V. Viñals and M. Valero. Speculative Early Register Release. ACM International Conference on Computing Frontiers, Ischia, May 2-5, 2006 , May 2006.



T. Ramírez, M. Pajuelo, O. Santana and M. Valero. Kilo-instruction Processors, Runahead and Prefetching. ACM International Conference on Computing Frontiers, Ischia, May 2-5, 2006 , May 2006.



J. Alastruey, T. Monreal, V. Viñals and M. Valero , March 26-30, 2007. . Microarchitectural Support for Speculative Register Renaming. IPDPS07. IEEE International Parallel and Distributed Processing Sympsium. Long Beach, USA,
, March 2006.



Pericás, M., González, R., Cristal, A., Jiménez, D., and Valero, M.. A Decoupled Kilo Instruction Processor. 11th International Conference on High Performance Computer Architecture (HPCA 12), Austin, USA, February 2006.


M. Pericás, R. González, A. Cristal, D. Jiménez and M. Valero. A Decoupled Kilo-instruction Processor. IEEE HPCA, International Conference on High Performance Computer Architecture, Austin , February 2006.



J. Verdú, M. Nemirovsky, J. García ans M. Valero. Architectural Impact of Statefull Networking APPlications. ANCS-2005. IEEE and ACM Symposium on Architectures for Networking and Communications Systems, Princeton, New Jersey , October 2005.



Mauricio Alvarez, Esther Salami, Alex Ramirez, Mateo Valero. A Performance Characterization of High Definition Digital Video Decoding Using H.264/AVC. 2005 IEEE International Symposium on Workload Characterization (IISWC-2005), Austin, Texas, October 2005.



Friman Sanchez, Esther Salami, Alex Ramirez, Mateo Valero. Parallel Processing in Biological Sequence Comparison using General Purpose Processors. 2005 IEEE International Symposium on Workload Characterization (IISWC-2005), Austin, Texas, October 2005.



F. Sánchez, E. Salami, A. Ramírez and M.Valero . Parallel Processing in Biological Sequence Comparison using General Purpose Processors. IISWC, IEEE Internacional Symposium on Workload Characterization, Austin, Texas , October 2005.



M. A. Ramírez, A. Cristal, L. Villa, Alex V. Veidenbaum and M. Valero. A New Pointer-based Instruction Queue Design and Its Power-Performance Evaluation. Best paper Award. ICCD. IEEE International Conference on Computer Design, San José, USA , October 2005.



F. Cazorla, P. M. W. Knijnenburg, R. Sakellarious, E. Fernández, A. Ramirez and M. Valero. Architectural Support for Real-TimeTask Scheduling in SMT Processors. CASES 2005. International Conference on Compilers, Architecture and Synthesis for Embedded Systems, San José , October 2005.



Pericás, M., Cristal, A., González, R., and Valero, M.. Decoupled State-Execute Architecture. 6th International Symposium on High Performance Computer (ISHPC 2005), Nara, Japan, September 2005.


Pericás, M., Cristal, A., González, R., Jiménez, D. A., and Valero, M.. Exploiting Instruction Locality with a Decoupled Kilo Instruction Processor. 6th International Symposium on High Performance Computer (ISHPC 2005), Nara, Japan, September 2005.


J. Verdú, M. Nemirovsky, J. García ans M. Valero. Workload Characterization and Stateful Networking Aplications. ISHPC. International Symposium on High Performance Computers, Nara, Japan , September 2005.



M. Pericás, A. Cristal, R. González, D.A. Jiménez and M. Valero. Exploiting Instruction Locality with a Decoupled kilo-Instruction Processor. ISHPC. International Symposium on High Performance Computers, Nara, Japan , September 2005.



O. Santana, A. Ramírez and M. Valero. Multiple Stream Prediction. ISHPC. International Symposium on High Performance Computers, Best paper Award. Nara, Japan , September 2005.



Francisco J. Cazorla, Peter M.W. Knijnenburg, Rizos Sakellariou, Enrique Fernandez, Alex Ramirez and Mateo Valero. Architectural Support for Real-Time Task Scheduling in SMT Processors. International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES-2005), San Francisco, USA, September 2005.


Oliverio J. Santana, Alex Ramirez, Mateo Valero. Multiple Stream Prediction. 6th International Symposium on High Performance Computing (ISHPC-VI), Nara, Japan. Also appears as Lecture Notes on Computer Science , September 2005.


M. Moretó, C. Martínez, R. Beivide, E. Vallejo and M. Valero. Hierarchical Gaussian Topologies. ACACES 2005, Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems, Láquila, pp. 211-214. Academic Press, ISBN 90 382 0802 2 , July 2005.



J. Alastruey, T. Monreal, V. Viñals and M. Valero . . Efficient Register File Management in High-ILP Processors. ACACES 2005, Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems, Láquila, pp. 201-204. Academic Press, ISBN 90 382 0802 2 , July 2005.



T. Ramírez, M. Galluzzi, A. Cristal and M. Valero. Different Approaches using Kilo-Instruction Processors. ACACES 2005, Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems, Láquila, pp. 197-200. Academic Press, ISBN 90 382 0802 2 , July 2005.



M. Pericás, R. González, A. Cristal and M. Valero . Overcoming the Memor Wall with D-KIPs. ACACES 2005, Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems, Láquila, pp. 99-102. Academic Press, ISBN 90 382 0802 2 , July 2005.



Vallejo, E., Galluzzi, M., Cristal, A., Vallejo, F., Beivide, R., Stenström, P., Smith, J. E., and Valero, M.. Implementing Kilo Instruction Multiprocessors. 2005 IEEE Conference on Pervasive Services (ICPS-05), Santorini, Greece , July 2005.


Carmelo Acosta, Ayose Falcón, Alex Ramirez, Mateo Valero. A Complexity-Effective Simultaneous Multithreading Architecture. 34th International Conference on Parallel Processing (ICPP 2005), pp. 157-164. Oslo, Norway, June 2005.


E. Salami and M. Valero. A Vector-uSIMD-VLIW Architecture for Multimedia Applications. ICPP, IEEE International Conference on Parallel Processing, Oslo, Norway , June 2005.



R. González, A. Cristal, M. Pericás, A. Veidenbaum and M. Valero. An Asymmetric Clustered Processor based on Value Content. IEEE-ACM, International Conference on Supercomputing, Bost.on, USA , June 2005.



Friman Sánchez, Mauricio Alvarez, Esther Salamí, Alex Ramirez, Mateo Valero. On the Scalability of 1- and 2-Dimensional SIMD Extensions for Multimedia Applications . 2005 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS-2005), pp. 167-176. Austin, Texas, March 2005.


A. Pajuelo, A. González and M. Valero. Control-Flow Independence Reuse via Dynamic Vectorization. IPDPS05, IEEE-ACM 19th International Parallel and Distributed Processing Symposium, Denver, Colorado , January 2005.



A. Falcón, A. Ramírez and M. Valero. Effective Instruction Prefetching via Fetch Prestaging. IPDPS05. IEEE-ACM 19th International Parallel and Distributed Processing Symposium, Denver, Colorado , January 2005.



R. Holanda, J. Verdú, J. garcía and M. Valero. Performance Analysis of New Packet Trace Compression TCP Flow Clustering. ISPASS05. IEEE International Symposium on Performance Analisys of Systems and Software, Austin, Texas , January 2005.



Francisco J. Cazorla, Alex Ramirez, Mateo Valero, Enrique Fernández. Dynamically Controlled Resource Allocation in SMT Processors. 37th Annual International Symposium on Microarchitecture (MICRO-37), pp. 171-182. Portland, Oregon, December 2004.


F. Cazorla, A. Ramirez. E. Fernández and M. Valero . DCRA: Dynamically Controlled Resource Allocation in SMT Processors. Micro-37. IEEE-ACM “International Symposium on Microarchitecture, Portland , November 2004.



M. A. Ramírez, A. Cristal, L. Villa, Alex V. Veidenbaum and M. Valero. Instruction Wakeup Mechanism: Power and Timing Evaluation. CIC,s Research and Computing Science, series, Mexico. City. ISBN:970-36-0194-4, ISSN:1665-9899 , October 2004.



M. Ramírez, A. Cristal, A. Veidenbaum, L. Villa and M. Valero . Colas de Instrucciones Escalables y de Bajo Consumo para Procesadores Superescalares. ENC2004. Encuentro Internacional de Ciencias de la Computación, Colima, Mexico , September 2004.



Francisco J. Cazorla, Peter M.W. Knijnenburg, Rizos Sakellariou, Enrique Fernandez, Alex Ramirez and Mateo Valero. Feasibility of QoS for SMT by Resource Allocation. EuroPar Conference, pp. 535-540. Pisa, Italy. Also appears as Lecture Notes in Computer Science 3149, Springer-Verlag. , September 2004.


Francisco J. Cazorla, Peter M.W. Knijnenburg, Rizos Sakellariou, Enrique Fernandez, Alex Ramirez and Mateo Valero. Enabling SMT for Real-Time Embedded Systems. 12th European Signal Processing Conference (EUSIPCO), Vienna, Austria, September 2004.


O.J. Santana, A. Falcón, A. Ramírez and M. Valero. Stream Predictor Guided Instruction Decoding. XV Jornadas de Paralelismo, Almeria, Spain , September 2004.



Francisco J. Cazorla, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández, Alex Ramirez, Mateo Valero. Implicit vs. Explicit Resource Allocation in SMT Processors. 2004 Euromicro Symposium on Digital Systems Design (DSD 2004), pp. 44-51. Rennes, France, August 2004.


F. Cazorla, A. Ramirez. E. Fernández, P. W. Knijnenburg, R. Sakellariou and M. Valero. Throughput versus Quality of Service in SMT processors. Euromicro-DSD (Digital System Design), Invited paper. Rennes,  , August 2004.



A, Cristal, O. Santana and M. Valero . Maintaining Thousands In-Flight Instructions. Europar Conference. LNCS, Keynote paper. Pisa , August 2004.



Ayose Falcón, Jared Stark, Alex Ramirez, Konrad Lai, and Mateo Valero. Prophet/Critic Hybrid Branch Prediction. 31st Annual International Symposium on Computer Architecture (ISCA-31), Munich, Germany, June 2004.


R. González, A. Cristal, D. Ortega, A.V. Veidenbaum and M. Valero. A Content Aware Integer Register File Organisation. ISCA-31. IEEE-ACM International Symposium on Computer Architecture, Munich, Germany , June 2004.



A. Cristal, O. Santana and M. Valero .. A Comprehensive Description of Kilo-instruction Processor. CORE-2004,  ISBN: 970-36-0149-9, pp. 144-154. National Conference on Computation. Mexico City, Mexico. , May 2004.



M. Galluzzi, V. Puente, A. Cristal, R. Beivide. J.A. Gregorio and M. Valero. A First Glance at Kilo-instruction Based Multiprocessors. ACM International Conference on Computing Frontiers, Invited paper to the session “The Memory Wall Problem”. CF`04. Ischia, Italy , April 2004.



Francisco J. Cazorla, Peter M.W. Knijnenburg , Rizos Sakellariou, Enrique Fernandez, Alex Ramirez, Mateo Valero. Predictable Performance in SMT Processors. Computing Frontiers (CF'04), pp. 433-443. Isbn:1-58113-741-9 ACM Press. Ischia, Italy, April 2004.


Francisco J. Cazorla, Enrique Fernandez, Alex Ramirez, Mateo Valero. DCache Warn: An I-Fetch Policy To Increase SMT Efficiency. 18th International Parallel and Distributed Processing Symposium (IPDPS-2004), Santa Fe, New Mexico, April 2004.


A. Cristal, D. Ortega, J. Llosa and M. Valero. Out-of-order Commit Processors. HPCA-10. IEEE “International Conference on High-Performance Computer Architectures”,  Madrid, Spain , February 2004.



Ayose Falcon, Alex Ramirez, Mateo Valero. A Low-Complexity, High-Performance etch Unit for Simultaneous Multithreading Processors. 10th International Conference on High Performance Computer Architecture (HPCA-10), pp. 244-253. Madrid (Spain), February 2004.


Ayose Falcón, Alex Ramirez and Mateo Valero. A Low-Complexity, High-Performance Fetch Unit for Simultaneous Multithreading Processors. In 10th International Symposium on High Performance Computer Architecture (HPCA-10), pp. 244-253, Madrid (Spain),

, February 2004.



Francisco J. Cazorla, Enrique Fernandez, Alex Ramirez and Mateo Valero. Improving Memory Latency Aware Fetch Policies for SMT Processors . Tokyo, Japan, Best student paper award. , October 2003.
International Symposium on High Performance Computing (ISHPC-V)


Ayose Falcón, Oliverio J. Santana, Alex Ramirez and Mateo Valero. Tolerating branch predictor latency on SMT. In 5th International Symposium on High Performance Computing (ISHPC-V), pp. 86-98, Tokio (Japan),

, October 2003.



Peter Knijnenburg, Alex Ramirez, Josep-L. Larriba-Pey and Mateo Valero. Branch classification for SMT fetch gating. In 6th Workshop on Multithreaded Execution, Architecture and Compilation (MTEAC6), Istambul (Turkey),
, November 2002.



Hans Vandierendonck, Alex Ramirez, Koenraad De Bosschere and Mateo Valero. A comparative study of redundancy in trace caches. In Intl. Euro-Par Conference, pp. 512-516, Paderborn (Germany),
, August 2002.



Oliverio J. Santana, Ayose Falcón, Enrique Fernández, Pedro Medina, Alex Ramirez and Mateo Valero. A Comprehensive Analysis of Indirect Branch Prediction. In 4th International Symposium on High Performance Computing (ISHPC-4), pp. 133-14, Kansai Science City (Japan).,
, June 2002.



Ayose Falcón, Oliverio J. Santana, Pedro Medina, Enrique Fernández, Alex Ramirez and Mateo Valero. Studying New Ways for Improving Adaptive History Length Branch Predictors. In 4th International Symposium on High Performance Computing (ISHPC-4), pp. 271-279, Kansai Science City (Japan),

, May 2002.



Alex Ramirez, Oliverio J. Santana, Josep-L. Larriba-Pey and Mateo Valero. Fetching Instruction Streams. In 35th Annual International Symposium on Microarchitecture (MICRO-35), pp. 371-382, Istambul (Turkey),

, January 2002.



Alex Ramirez, Josep-L. Larriba-Pey and Mateo Valero. Branch Prediction Using Profile Data. In 7th International Euro-Par Conference (Euro-Par'2001), pp. 386-393, Manchester (United Kingdom),

, August 2001.



Alex Ramirez, Luiz A. Barroso, Kourosh Gharachorloo, Robert Cohn, Josep-L. Larriba-Pey, Geoffrey Lowney and Mateo Valero. Code Layout Optimizations for Transaction Processing Workloads. In 28th Annual International Symposium on Computer Architecture (ISCA-28), pp. 155-164, Göteborg (Sweden),
, June 2001.



Miquel Pericàs, Ruben Gonzalez, Adrian Cristal, Francisco J. Cazorla, Daniel A. Jimenez and Mateo Valero. A Flexible Heterogeneous Multi-Core Architecture . PACT-16, , November 1999.



Miquel Pericàs, Ricardo Chaves, Georgi N. Gaydadjiev, Mateo Valero and Stamatis Vassiliadis. Vectorized AES Core for high-throughput secure environments. VECPAR'08, , November 1999.



Miquel Pericas, Adrian Cristal, Ruben Gonzalez, Alex Veidenbaum, Daniel A. Jimenez and Mateo Valero. A two-level Load/Store Queue based on Execution Locality . The 35th International Symposium on Computer Architecture (ISCA-35), , November 1999.



National Conferences

Alejandro Rico, Alex Ramirez and Mateo Valero. Task Management Analysis on the Cell BE. In XIX Jornadas de Paralelismo, pp. 271-276, Castellón (Spain),

, September 2008.



Miquel Moreto, Francisco J. Cazorla, Alex Ramirez and Mateo Valero . Online Prediction of Throughput for Different Cache Sizes. XVIII Jornadas de Paralelismo. Zaragoza, Spain,
, September 2007.



Felipe Cabarcas, Alejandro Rico, David Rodenas, Xavier Martorell, Alex Ramirez and Eduard Ayguadé. CellSim: A Validated Modular Heterogeneous Multiprocessor Simulator. In XVIII Jornadas de Paralelismo de Zaragoza, pp. 181-188, Zaragoza (Spain),

, September 2007.



I. González, O.J. Santana, A. Pajuelo, M. Valero 18-20 Septiembre, 2006. Implementando recuperaciones precisas en procesadores con consolidación fuera de orden. XVII Jornadas de Paralelismo, Albacete, Spain , September 2006.



C. Boneti, F. Cazorla, M. Valero . Improving EDF for SMT processors. XVII Jornadas de Paralelismo, Albacete, Spain , September 2006.



K. Kedzierski, F. Cazorla, M. Valero . . Analysis of multithreading capabilities of current high-performance processors. XVII Jornadas de Paralelismo, Albacete, Spain , September 2006.



J. Vera, F.J. Cazorla, A. Pajuelo, O.J. Santana, E. Fernández, M. Valero . Looking for novel ways to obtain fair measurements in multithreaded architectures. XVII Jornadas de Paralelismo, Albacete, Spain , September 2006.



Vallejo, E., Galluzzi, M., Cristal, A., Vallejo, F., Beivide, R., Stenström, P., Smith, J. E., and Valero, M.. KIMP: Multicheckpointing Multiprocessors. XVI Jornadas de Paralelismo, Granada, Spain, September 2005.


García, A., Medina, P., Fernández, E., Santana, O., Cristal, A., and Valero. M.. Towards the Loop Processor Architecture. XVI Jornadas de Paralelismo, Granada, Spain, September 2005.


Ramírez, T., Cristal, A., Santana, O., Pajuelo, A., and Valero, M. . Eficacia versus Eficiencia: Una Decisión de Diseño en Runahead. XVI Jornadas de Paralelismo, Granada, Spain, September 2005.


J. Verdu, M. Nemirosvky, J. García and M. Valero. Workload Analysis of Networking Applications. XVI Jornadas de Paralelismo, Granada, Spain , September 2005.



F. Cazorla, E. Fernández, A. Ramírez and M. Valero. Dynamically Controlled Resource Allocation in SMT. XVI Jornadas de Paralelismo. Granada, Granada, Spain , September 2005.



M. Moreto, C. Martínez, E. Vallejo, M. Beivide and M. Valero . Hierarchical Topologies for Large-Scale Two-Level Networks. XVI Jornadas de Paralelismo, Granada, Spain , September 2005.



R. González, A. Cristal, M. Pericas, A. Veidenbaum and M. Valero. Arquitectura Simétrica Clusterizada basada en el Contenido. XVI Jornadas de Paralelismo, Granada, Spain , September 2005.



C. Acosta, A. Falcón, A. Ramírez and M. Valero. hdSMT: An Heterogeneity-Aware Simultaneous Multithreaded Architecture. XVI Jornadas de Paralelismo, Granada, Spain , September 2005.



O. Santana, A. Ramírez and M. Valero. Predicting two Streams per Cycle. XVI Jornadas de Paralelismo, Granada, España , September 2005.



S. Mir, F. Cazorla, A, Ramirez and M. Valero. Metrics for the Evaluation of SMT Processors Performance. XVI Jornadas de Paralelismo, Granada, Spain , September 2005.



A. Falcón, O. Santana, A. Ramírez and M. Valero . SelectingWhere to Simulate SPEC2000 Using Streams Analysis. XV Jornadas de Paralelismo, Almeria, Spain , September 2004.



X. Verdú, J. García, M. Nemirovsky and M. Valero. Analysis of Traffic Traces for Statefull Applications. XV Jornadas de Paralelismo, Almeria, Spain , September 2004.



M. Alvarez, F. Sánchez, E. Salami, A. Ramírez and M. Valero. Scalability and Complexity of 2-Dimensional SIMD Extensions. XV Jornadas de Paralelismo, Almeria, Spain , September 2004.



A. Pajuelo, A. González and M. Valero . Aggressive Speculative Execution for Hidding Memory Latency. XV Jornadas de Paralelismo, Ameria, Spain , September 2004.



M. Galluzzi, V. Puente. O.J. Santana, C. Acosta, A. Cristal, M. Beivide, J.A. Gregorio and M. Valero . Introducing Kilo-Instruction Multiprocessor. XV Jornadas de Paralelismo, Alemria, Spain , September 2004.



J. Alastruey, T. Monreal, V. Viñals and M. Valero. Limits on Early Release of Physical Registers. XV Jornadas de Paralelismo, Alemeria, Spain , September 2004.



C. Acosta, A. Falcón, A. Ramírez and M. Valero. Heterogeneity-Aware Architectures. XV Jornadas de Paralelismo, Almeria, Spain , September 2004.



C. Acosta, M. Galluzzi, S. Vajapeyam, A. Ramírez and M. Valero. Dealing with Billions of Transistors. XIV Jornadas de Paralelismo, Madrid, Spain , September 2003.



Oliverio J. Santana, Marco Galluzzi, Alex Ramirez and Mateo Valero. An Analysis of Dynamic Instruction Streams. In XIV Jornadas de Paralelismo, pp. 527-532, Leganés (Spain),
, September 2003.



Francisco J. Cazorla, Pedro Medina, Enrique Fernández, Alex Ramirez and Mateo Valero. Estudio y evaluación de mecanismos de control de la Especulación. In XIII Jornadas de Paralelismo, Lleida (Spain),

, September 2002.



Alejandro Garcia, Enrique Fernández, Pedro Medina, Alex Ramirez and Mateo Valero. Analisis y caracterización de los bucles. In XIII Jornadas de Paralelismo, Lleida (Spain),
 

, September 2002.



Ayose Falcón, Oliverio J. Santana, Pedro Medina, Enrique Fernández, Alex Ramirez and Mateo Valero. An Analysis of Dynamic History Length Fitting. In XII Jornadas de Paralelismo, Valencia (Spain),
, September 2001.



Oliverio J. Santana, Ayose Falcón, Enrique Fernández, Pedro Medina, Alex Ramirez and Mateo Valero. An In-Depth Evaluation of the Multi-Stage Cascaded Predictor. In XII Jornadas de Paralelismo, Valencia (Spain),

, September 2001.



Workshops

Sebastián Isaza, Friman Sánchez, Georgi Gaydadjiev, Alex Ramirez and Mateo Valero. Scalability Analysis of Progressive Alignment in a Multicore. In International Workshop on Multi-Core Computing Systems (MuCoCoS 2010), Krakow (Poland),


, February 2010.



Ferad Zyulkyarov , Sanja Cvijic, Osman Unsal , Adrian Cristal , Eduard Ayguade, Tim Harris , Mateo Valero. WormBench - A Configurable Workload for Evaluating Transactional Memory Systems. Workshop on MEmory performance: DEaling with Applications, systems and architecture (MEDEA), in conjunction with PACT, , October 2008.



Vladimir Cakarevic, Petar Radojkovic, Javier Verdu, Alejandro Pajuelo, Roberto Gioiosa, Francisco J. Cazorla, Mario Nemirovsky and Mateo Valero. Understanding the Overhead of the Spin-lock Loop in CMT Architectures. Bejing, China, In Workshop on the Interaction between Operating Systems and Computer Architecture (WIOSCA)


, June 2008.
Barcelona Supercomputing Center


Carlos Villavieja ,Isaac Gelado ,Alex Ramirez ,Nacho Navarro. Memory Management on Chip-MultiProcessors with on-chip Memories. Workshop on the Interaction between Operating Systems and Computer Architecture (WIOSCA'08), , June 2008.



Carlos Villavieja, Isaac Gelado, Alex Ramirez and Nacho Navarro. On-Chip memories, the OS perspective. In 5th HiPEAC Industrial Workshop, Barcelona (Spain),

, June 2008.



Enrique Vallejo, Sutirtha Sanyal, Tim Harris, Fernando Vallejo, Ramón Beivide, Osman Unsal, Adrián Cristal, Mateo Valero. Towards fair, scalable, locking. Workshop on Exploiting Parallelism with Transactional Memory and other Hardware Assisted Methods (EPHAM 2008) in conjunction with GCO, , April 2008.



Pedro A. Castillo, Antonio M. Mora, Juan Julian Merelo, Juan Luis J. Laredo, Miquel Moreto, Francisco J. Cazorla, Mateo Valero and Sally A. McKee. Architecture performance prediction using evolutionary artificial neural networks. European Workshop on Hardware Optimization Techniques (EVOHot), , March 2008.



Enrique Vallejo, Tim Harris, Adrian Cristal, Osman Unsal, Mateo Valero. Hybrid Transactional Memory to Accelerate Safe Lock-based Transactions. Third ACM SIGPLAN Workshop on Transactional Computing TRANSACT, , February 2008.



Cor Meenderinck, Arnaldo Azevedo, Mauricio Alvarez, Ben Juurlink, Alex Ramirez. Parallel Scalability of H.264. 1st Workshop on Programmability Issues for Multi-Core Computers (MULTIPROG), , January 2008.



Miloš Milovanović, Roger Ferrer, Vladimir Gajinov, Osman S. Unsal, Adrian Cristal, Eduard Ayguadé, MateoValero. Multithreaded Software Transactional Memory and OpenMP. Workshop on Memory performance: Dealing with Applications, systems and architecture (Medea) in conjunction with PACT, , September 2007.



Ferad Zyulkyarov, Osman S. Unsal, Adrian Cristal, Milos Milovanovic, Eduard Ayguade, Mateo Valero, Tim Harris. Memory Management for Transaction Processing Core in Heterogeneous Chip Multiprocessors. Workshop on Operating System support for Heterogeneous Multicore Architectures (OSHMA) in conjunction with PACT, , September 2007.



Sasa Tomic, Adrian Cristal, Osman Unsal, Mateo Valero. Hardware Transactional Memory with Operating System Support, HTMOS. Workshop on Highly Parallel Processing on a Chip in conjunction with Euro-Par - LNCS 4854, , August 2007.



Cristian Perfumo, Nehir Sonmez, Osman S. Unsal, Adrian Cristal, Mateo Valero, Tim Harris. Dissecting Transactional Executions in Haskell. Second ACM SIGPLAN Workshop on Transactional Computing TRANSACT, , August 2007.



Paul Carpenter, David Rodenas, Xavier Martorell, Alex Ramirez, Eduard Ayguade. A Streaming Machine Description and Programming Model. 7th Intl. Workshop on Embedded Computer Systems: Architectures, MOdeling, and Simulation (SAMOS VII), , July 2007.



Milos Milovanovic, Roger Ferrer, Osman S. Unsal, Adrian Cristal, Eduard Ayguade, Jesus Labarta, Mateo Valero. Transactional Memory and OpenMP. International Workshop on OpenMP, , June 2007.



Alejandro Rico, Felipe Cabarcas, David Rodenas, Xavier Martorell, Alex Ramirez, Eduard Ayguade. Implementation and Validation of a Cell Simulator unsing UNISIM. 3rd HiPEAC Industrial Workshop, , April 2007.



C. Acosta, F.J.Cazorla, A. Ramírez and M. Valero. Core to Memory Interconnection Implications for Forthcoming On-Chip Multiprocessors. 1st Workshop on Chip Multiprocessor Memory Systems and Interconnects (CMP-MSI 2007), Phoenix, USA.  , February 2007.



Milos Milovanovic, Osman S. Unsal, Adrian Cristal, Srdan Stipic, Ferad Zyulkyarov, Mateo Valero. Compile Time Support for Using Transactional Memory in C/C++ Applications. 11th Annual Workshop on the Interaction between Compilers and Computer Architecture INTERACT, , February 2007.



A. Ramírez, O. Prat, J. Labarta and M. Valero , on Sunday, January 2007. . Performance Impact of the Interconnection Network on MareNostrum Applications. HiPEAC Workshop on Interconnection Network Architectures: On-Chip, Multi-Chip, Ghent, Belgium, in conjunction with the HiPEAC'07 Conference , January 2007.



J. Vera, F. J. Cazorla, A. Pajuelo, O. J. Santana, E. Fernandez and M. Valero . Measuring the Performance of Multithreaded Processors. SPEC 2007 Benchmark Workshop, Austin, USA , January 2007.



T. Ramírez, M. Pajuelo, O. Santana and M. Valero. A Simple Speculative Load Control Mechanism for Energy Saving. MEDEA Workshop: “MEmory performance:DEaling with Applications, systems and architecture”, Held in conjuction with PACT 2006 in Seattle, USA , September 2006.



Ramírez, T., Galluzzi, M., Cristal, A., and Valero, M.. Different Approaches using Kilo Instruction Processors. 1st International Summer School on Advanced Computer Architecture and Compilation for Embedded Systems (ACACES 2005), (Láquila, Italy). Academic Press, ISBN 90 382 0802 2., July 2006.


Pericás, M., González, R., Cristal, A., and Valero, M.. Overcoming the Memory Wall with D-KIPs. 1st International Summer School on Advanced Computer Architecture and Compilation for Embedded Systems (ACACES 2005), (Láquila, Italy). Academic Press, ISBN 90 382 0802 2., July 2006.


J. Vera, F. Cazorla, A. Pajuelo, O.J. Santana, E. Fernández and M. Valero . A Novel Evaluation Methodology to Obtain Fair Measurements in Multithreaded Architectures . Boston, USA, In conjunction with ISCA, June 2006.
MoBS-2, Workshop on Modeling, Benchmarking and Simulation


A. Pajuelo, A. González and M. Valero. Speculative Execution for Hiding Memory Latency. MEDEA 2004 Workshop, Computer Architecture News, Vol. 33, No. 3, Special Issue: , pp. 49-56. , June 2005.



X. Verdú, M. Nemirosvky, J. García and M. Valero. Te Impact of Traffic Aggregation on the Memory Performance of Networking Applications. Computer Architecture News, Vol. 33, No. 3. Special Issue: MEDEA 2004 Workshop, pp.57-62 , June 2005.



M. Pericàs, R. González, A. Cristal, A. Veidenbaum and M. Valero. An Optimized Front-End Physical Register File with Banking and Writeback Filtering. PACS´04. Workshop on Power-Aware Computer Systems, In conjuction with Micro-37. IEEE-ACM “International Symposium on Microarchitecture”. Portland , December 2004.



A. Pajuelo, A. González and M. Valero . Speculative Execution for Hiding Memory Latency. MEDEA Workshop: “MEmory performance:DEaling with Applications, systems and architecture, Held in conjuction with PACT 2004 in Antibes, France , September 2004.



X. Verdú, M. Nemirosvky, J. García and M. Valero . Traffic Aggregation Impact on the Memory Performance of Networking Applications. MEDEA Workshop: “MEmory performance:DEaling with Applications, systems and architecture”, Held in conjuction with PACT  2004 in Antibes, France. , September 2004.



Oliverio J. Santana, Ayose Falcón, Alex Ramirez, and Mateo Valero. A Complexity-Effective Decoding Architecture Based on Instruction Streams. Workshop on Complexity-Effective Design (WCED), (in conjunction with 31st Annual International Symposium on Computer Architecture (ISCA-31)). Munich, Germany, June 2004.


Francisco J. Cazorla, Enrique Fernandez, Alex Ramirez, Mateo Valero. Approaching a Smart Sharing of Resources in SMT Processors. Workshop on Complexity-Effective Design (WCED), (in conjunction with 31st Annual International Symposium on Computer Architecture (ISCA-31)). Munich, Germany, June 2004.


J. García, M. March, L. Cerdá, J. Corbal and M. Valero . A Hybrid DRAM/SRAM Design for Fast Packet Buffers. HPRS. IEEE Workshop on High Performance Switching and Routing, Phoenix, Arizona , April 2004.



A. Cristal, J. Martínez. J. Llosa and M. Valero. A Case for Resource Conscious Out-of-Order Processor: Towards Kilo-instructions in-flight Processors. MEDEA Workshop,

ACM Computer Architecture News. Special Issue: MEDEA Workshop

, March 2004.



M. March, J. García, Ll. Cerdá and M. Valero . Analysis of a high performance DRAM/SRAM memory scheme for fast packet buffers. WEPA-1: Workshop on Embedded Parallel Architectures at HPCA-10, Madrid, Spain , February 2004.



J. Verdú, J. García, M. Nemirovsky and M. Valero. Analysis of Traffic Traces for Stateful Applications. NP3 : Third Workshop on Network Processors and Applications at HPCA-10, Madrid, Spain , February 2004.



Oliverio J. Santana, Alex Ramirez, and Mateo Valero. Reducing Fetch Architecture Complexity Using Procedure Inlining. 8th Workshop on Interaction between Compilers and Computer Architectures (INTERACT), (in conjunction with 10th Intl. Conference on High Performance Computer Architecture (HPCA-10)). Madrid, Spain, February 2004.


M. A. Ramirez, A. Cristal, A. V. Veidenbaum, L. Villa and M. Valero. Direct Instruction Wakeup for OoO Procesors. IWIA. International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems, Maui, Hawwaii , January 2004.



Oliverio J. Santana, Alex Ramirez and Mateo Valero. Latency Tolerant Branch Predictors. In 2003 International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'03), pp. 30-39, Kauai, Hawaii (United States),
, July 2003.



C. Acosta, S. Vajapeyam, A. Ramírez and M. Valero. CDE: A Compiler-driven, Dependence-Centric, Eager-executing Architecture for the Billion Transistors Era. Workshop on Complexity-Effective Design (WCED 2003), San Diego, USA. , June 2003.



Peter Knijnenburg, Alex Ramirez, Fernando Latorre, Josep-L. Larriba-Pey and Mateo Valero. Branch Classification to Control Instruction Fetch in Simultaneous Multithreaded Architectures. International Workshop on Innovative Architecture (IWIA 2002), pp. 67-76, Kohala Coast, Hawaii (United States),

, August 2002.



Peter Knijnenburg, Alex Ramirez, Fernando Latorre, Josep-L. Larriba-Pey and Mateo Valero. Branch Classification to Control Instruction Fetch in Simultaneous Multithreaded Architectures. In 2002 International Workshop on Innovative Architecture (IWIA 2002), pp. 67-76, Kohala Coast, Hawaii (United States),
, August 2002.



Marsha Eng, Hong Wang, Perry Wang, Alex Ramirez, J. Fung and John Shen. Mesocode: Optimizations for Improving Fetch Bandwidth of Itanium Processors. In Workshop on Complexity-Effective Design, Anchorage, AK (United States),

, June 2002.



Communications

Mauricio Álvarez, Alex Ramirez, Xavier Martorell, Eduard Ayguadé and Mateo Valero. Scalability of Macroblock-level Parallelism for H.264 Decoding. In Advanced Computer Architecture and Compilation for Embedded Systems. ACACES 2008, Poster,
, July 2008.



Friman Sánchez, Alex Ramirez and Mateo Valero. Parallelization Strategies for Smith Waterman Algorithm on CellBE. In Advanced Computer Architecture and Compilation for Embedded Systems. ACACES 2008, Poster Session, pp. 147-150, L'Aquila (Italy),

, July 2008.



Augusto J. Vega, Alex Ramirez and Mateo Valero. 3D Die-Stacking Architectures: State of the Art. In Advanced Computer Architecture and Compilation for Embedded Systems. ACACES 2008, pp. 203-207, L'Aquila (Italy),
, July 2008.



Felipe Cabarcas, Alejandro Rico, David Rodenas, Xavier Martorell, Alex Ramirez and Eduard Ayguadé. CellSim: A Cell Processor Simulation Infrastructure. In 2007 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES),
, July 2007.



M. Moreto, A. Ramírez and M. Valero . Reducing Simulation Time. ACACES 2006, Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems, Láquila, pp. 233-236. Academia Press, ISBN 90 382 0981 9 , July 2006.



Mateo Valero. Kilo-instruction Processors: Overcoming the Memory Wall. University of Irvine at California,
, February 2006.



M. Alvarez, E. Salami, A. Ramírez and M. Valero . A Performance Evaluation of High Definition Digital Video Decoding Using the H.264/AVC Standard. ACACES 2005, Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems, Láquila, pp. 255-258. Academic Press, ISBN 90 382 0802 2 , July 2005.



F. Cazorla, P. M. W. Knijnenburg, R. Sakellarious, E. Fernández, A. Ramirez and M. Valero. Quality of service for Simultaneous Multithreading Processors. ACACES 2005, Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems, Láquila, pp. 67-70. Academic Press, ISBN 90 382 0802 2 , July 2005.



C. Acosta, A. Falcón, A. Ramírez and M. Valero . Complexity-Effectiveness in Multithreadind Architectures. ACACES 2005, Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems, Láquila, pp. 79-82. Academic Press, ISBN 90 382 0802 2 , July 2005.



Carmelo Acosta, Ayose Falcón, Alex Ramirez and Mateo Valero. Complexity-Effectiveness in Multithreading Architectures. In 2005 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-2005), Poster Session, pp. 79-82, L'Aquila (Italy),

, July 2005.



F. Sánchez, E. Salami, A. Ramírez and M. Valero . Parallel Processing in Sequence Matching. ACACES 2005, Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems, Láquila, pp. 279-282. Academic Press, ISBN 90 382 0802 2 , January 2005.



Felipe Cabarcas, Alejandro Rico, David Rodenas, Xavier Martorell, Alex Ramirez ,Eduard Ayguade. A module based Cell processor simulator. ACACES 2006 Poster Session, , July 2006.