Computer Architecture for Parallel Paradigms

Overview: 

For processor manufacturers, the traditional approach of increasing performance through exploiting Instruction Level Parallelism (ILP) has hit the power wall; so they are shifting to the less complex approach of utilizing Thread Level Parallelism (TLP). By including more processing cores on chip, total processor throughput is increased through exploiting TLP and parallel computing. However, substantial challenges lay ahead on proper hardware and architecture support for the system stack and the parallel programmed ecosystem of the future. The research group conducts research in developing hardware support to fully utilize future many-cores and to make them easier to program and debug.

The group is involved in running the BSC-Microsoft Research Centre and collaborates with Microsoft researchers.

Objectives: 

We believe that in the era of many-core chips, the software community (OS, Compiler, Programming Model, Applications) must be in the driver seat. In tandem with this new reality, the overall objective of the group is to conduct research in top-down Computer Architecture by designing hardware for software. Our overall objectives is making many-core processors easirt to program. More specifically we conduct research on:
•    Transactional Memory (TM) is a technology which promises to make shared-memory programming easier. The team proposes hardware support for accelerating Software Transactional Memory (STM), designs scalable Hardware Transactional Memory (HTM) implementations, produces TM applications and benchmarks, investigates TM use in system libraries, proposes power/aware TM heuristics and develops TM debuggers.
•    Hardware support for providing easier to use and fair locking implementations.    
•    Hardware support for managed language runtimes such as Haskell or C#.
•    Developing power and complexity aware architectures for small form-factor high-performance computing systems.

Projects/Areas: 

The research group has coordinated VELOX, an FP7 research project in Transactional Memory.
More information is available at: http://www.velox-project.eu

The group is involved in running the BSC-Microsoft Research Centre

PEOPLE

PUBLICATIONS AND COMMUNICATIONS

2011

Arcas, O., Sönmez, N., Unsal, O., Cristal, A. & Valero, M. A Flexible Hybrid Transactional Memory Multicore on FPGA. Jornadas de Paralelismo 2011 283–289 (2011).
Villavieja, C., et al. DiDi: Mitigating The Performance Impact of TLB Shootdowns Using A Shared TLB Directory. Parallel Architectures and Compilation Techniques (PACT) (2011).
Armejach, A., et al. Using a Reconfigurable L1 Data Cache for Efficient Version Management in Hardware Transactional Memory. Parallel Architectures and Compilation Techniques (PACT) 360–370 (2011).
Yalcin, G., Unsal, O., Cristal, A. & Valero, M. FIMSIM: A fault injection infrastructure for microarchitectural simulators. 29th International Conference on Computer Design (ICCD) 431–432 (2011).
Tomić, S., Cristal, A., Unsal, O. & Valero, M. Rapid Development of Error-Free Architectural Simulators using Dynamic Runtime Testing. 23rd International Symposium on Computer Architecture and High Performance Computing (2011).
Yalcin, G., Unsal, O., Cristal, A., Hur, I. & Valero, M. SymptomTM: Symptom Based Error Detection and Recovery Using Hardware Transactional Memory. Parallel Architectures and Compilation Techniques (PACT) 199–200 (2011).
Yalcin, G., Unsal, O., Cristal, A. & Valero, M. FaulTM-multi: Fault Tolerance for Multithreaded Applications Running on Transactional Memory Hardware. Workshop on Wild and Sane Ideas in Speculation and Transactions (2011).
Seyedi, A., et al. Circuit Design of a Dual-Versioning L1 Data Cache for Optimistic Concurrency. 21st Great Lakes Symposium on Very Large Scale Integration (GLSVLSI'11) (2011).
Sönmez, N., et al. TMbox: A Flexible and Reconfigurable 16-core Hybrid Transactional Memory System. The 19th Annual IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM 2011) 1–8 (2011).
Kestor, G., et al. RMS-TM: A Comprehensive Benchmark Suite for Transactional Memory Systems. International Conference on Performance Engineering (ICPE 2011) (2011).

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