Computer Architecture for Parallel Paradigms

Overview: 

For processor manufacturers, the traditional approach of increasing performance through exploiting Instruction Level Parallelism (ILP) has hit the power wall; so they are shifting to the less complex approach of utilizing Thread Level Parallelism (TLP). By including more processing cores on chip, total processor throughput is increased through exploiting TLP and parallel computing. However, substantial challenges lay ahead on proper hardware and architecture support for the system stack and the parallel programmed ecosystem of the future. The research group conducts research in developing hardware support to fully utilize future many-cores and to make them easier to program and debug.

The group is involved in running the BSC-Microsoft Research Centre and collaborates with Microsoft researchers.

Objectives: 

We believe that in the era of many-core chips, the software community (OS, Compiler, Programming Model, Applications) must be in the driver seat. In tandem with this new reality, the overall objective of the group is to conduct research in top-down Computer Architecture by designing hardware for software. Our overall objectives is making many-core processors easirt to program. More specifically we conduct research on:
•    Transactional Memory (TM) is a technology which promises to make shared-memory programming easier. The team proposes hardware support for accelerating Software Transactional Memory (STM), designs scalable Hardware Transactional Memory (HTM) implementations, produces TM applications and benchmarks, investigates TM use in system libraries, proposes power/aware TM heuristics and develops TM debuggers.
•    Hardware support for providing easier to use and fair locking implementations.    
•    Hardware support for managed language runtimes such as Haskell or C#.
•    Developing power and complexity aware architectures for small form-factor high-performance computing systems.

Projects/Areas: 

The research group has coordinated VELOX, an FP7 research project in Transactional Memory.
More information is available at: http://www.velox-project.eu

The group is involved in running the BSC-Microsoft Research Centre

PEOPLE

PUBLICATIONS AND COMMUNICATIONS

2013

Smiljković, V., Nowack, M., Miletić, N., Harris, T., Unsal, O., Cristal, A. & Valero, M. TM-dietlibc: A TM-aware Real-world System Library. The 27th IEEE International Parallel and Distributed Processing Symposium (IPDPS) (2013).
Smiljković, V., Stipić, S., Unsal, O., Cristal, A. & Valero, M. Transaction Coalescing - Lowering Transactional Overheads by Merging Transactions. Sixth Workshop on Programmability Issues for Heterogeneous Multicores (MULTIPROG-2013) (2013).
Tomić, S., Akpinar, E., Cristal, A., Ünsal, O.S. & Valero, M. EcoTM: Conflict-Aware Economical Unbounded Hardware Transactional Memory. International Conference on Computational Science, ICCS 2013 (2013).
ivan Ratkovic,, Palomar, O., milan stanic,, Ünsal, O.S., Cristal, A. & Valero, M. On the Selection of Adder Unit in Energy Efficient Vector Processing. ISQED (2013).

2012

Stipić, S., Tomić, S., Zyulkyarov, F., Cristal, A., Ünsal, O.S. & Valero, M. TagTM - accelerating STMs with hardware tags for fast meta-data access. DATE 39-44 (2012).
Tomić, S., Cristal, A., Unsal, O. & Valero, M. Using Dynamic Runtime Testing for Rapid Development of Architectural Simulators. International Journal of Parallel Programming (2012).
Gajinov, V., Stipić, S., Unsal, O., Harris, T., Ayguadé, E. & Cristal, A. Integrating Dataflow Abstractions into the Shared Memory Model. Computer Architecture and High Performance Computing (SBAC-PAD), 2012 IEEE 24th International Symposium on 243–251 (2012).
Negi, A., Armejach, A., Cristal, A., Unsal, O. & Stenström, P. Transactional prefetching: narrowing the window of contention in hardware transactional memory. Parallel Architectures and Compilation Techniques (PACT) 181-190 (2012).
Hayes, T., Palomar, O., Unsal, O., Cristal, A. & Valero, M. Vector Extensions for Decision Support DBMS Acceleration. The 45th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO45) 166-176 (2012).doi:10.1109/MICRO.2012.24
Gajinov, V., Stipić, S., Unsal, O.S., Harris, T., Ayguadé, E. & Cristal, A. Supporting Stateful Tasks in a Dataflow Graph. Proceedings of the 21st international conference on Parallel architectures and compilation techniques 435–436 (2012).

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