Computer Architecture

Overview: 

Computer Architecture is about designing the internal organization of a computer system to meet a given set of requirements as efficiently as possible within economic and technological limits. Simply adding more resources to a computer system does not make it any faster. Organizing them in the right way so that they can be used efficiently and in a collaborative manner is what makes a faster computer. Design alternatives appear at all levels of a computer system, from the internal processor configuration, to the integration board, to the whole system interconnection. Finding the right balance between all design options, and proposing new design alternatives is the task of the computer architect.

Objectives: 

The Computer Architecture group deals mostly with the processing part of a system design. Our objectives are:

  • To propose new processor designs that provide higher computing performance at lower energy cost. Research on processor microarchitecture techniques that efficiently exploit different levels of parallelism; either instruction level parallelism (ILP), data level parallelsim (DLP), or thread level parallelsim (TLP).
  • To propose and develop novel design methodologies that enable researchers to explore the huge design sapce represented by future computer architectures. Research on processor performance prediction models and simulation methodologoes for heterogeneous on-chip multiprocessor systems.
  • To propose new processor organizations that efficiently combine multiple processing untis in a single chip. Research on new application specific compute engines, the memory organization of multiprocessor chips, the communication protocols and their architecture support for the different on-chip structures.
Projects/Areas: 
  • Architectures to exploit Thread Level Parallelism: There are many possible architectures that execute multiple threads in a single chip ranging from one processor for each thread, to all threads sharing the same processor. In any case, resources are shared among threads for better utilization. However, this means threads also compete for them. This task deals with scheduling threads and partitioning resources for optimum execution efficiency.
  • Architectures to exploit Instruction Level Parallelism: Even state of the art compilers have difficulties extracting thread level parallelsim automatically. However, they are very efficient at extracting instruction level parallelism. Supescalar and out-of-order processors exploit this parallelism to increase single-thread performance. This task deals with proposing novel, more efficient, implementations of ILP processors.
  • Application specific accelerators: Current high performance processor architectures have been tailored to increase performance of a subset of applications deemed representative of what user will run on them. This includes compilers, floating-point arithmetic applicaions. compression codes, simulators. There is a wide range of end-user applications that have execution characteristics that do not follow the same trends,a nd that could benefit from a similar tailor-made design. This task deals with identifications of the most important emerging applications, analysis of their execution, and custom architecture design.
  • Architecture support for parallel programming models: Processor architects and programming model architects represent two largely decoupled communities. First processor architects design a product, add a series of high performance features, and leave it to the programming model to find out how to actually use them. This task deals with bridging the gap between both, and designing the processor in the opposite directions: first find out what the programming model can efficiently use, and add support fo it in the architecture.
  • Design space exploration: A new architecture design involves a number of tightly interconnected elements: the processor, the compiler, the runtime system. Any change in the architecure means changing the compiler and runtime system. Furthermore, when designing a new architecture, there is a huge design space that has to be explored searching for the best options. This task is about developing new tools and methodologies that allow an efficient design space exploration, while maintining all parts of the architeture in sync with each other.

PEOPLE

PUBLICATIONS AND COMMUNICATIONS

2012

Hussain, T., Shafiq, M., Pericàs, M., Nacho, N. & Ayguadé, E. PPMC : A Programmable Pattern based Memory Controller. Applied Reconfigurable Computing (ARC) 1–12 (2012).
Rico, A., et al. On the Simulation of Large-scale Architectures Using Multiple Application Abstraction Levels. ACM Transactions on Architecture and Code Optimization 8, 36 (2012).
González, S., et al. ReLA, a local alignment search tool for the identification of distal and proximal gene regulatory regions and their conserved transcription factor binding sites. Bioinformatics (2012).at <http://bioinformatics.oxfordjournals.org/content/28/6/763.long>
González, S., et al. Prediction of regulatory regions using ReLA". 16th Annual International Conference on Research in Computational Molecular Biology. 16th Annual International Conference on Research in Computational Molecular Biology, RECOMB (2012).

2011

Villavieja, C., et al. DiDi: Mitigating The Performance Impact of TLB Shootdowns Using A Shared TLB Directory. Parallel Architectures and Compilation Techniques (PACT) (2011).
Shafiq, M., Pericàs, M. & Ayguadé, E. A Template System for the Efficient Compilation of Domain Abstractions onto Reconfigurable Computers. 5th HiPEAC Workshop on Reconfigurable Computing (WRC 2011) 65–74 (2011).
Hussain, T., Pericàs, M. & Ayguadé, E. Reconfigurable Memory Controller with Programmable Pattern Support. 5th HiPEAC Workshop on Reconfigurable Computing (WRC 2011) 55–64 (2011).
Hussain, T., Pericàs, M., Nacho, N. & Ayguadé, E. Implementation of a Reverse Time Migration Kernel using the HCE High Level Synthesis Tool. Field Programmable Technology 1–8 (2011).
González, J., et al. Simulating Whole Supercomputer Applications. IEEE Micro 31, 32-45 (2011).
Isaza, S., Sánchez, F., Gaydadjiev, G., Ramirez, A. & Valero, M. Parameterizing Multicore Architectures for Multiple Sequence Alignment. 2011 International Conference on Computing Frontiers (2011).

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