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Vallejo, E. et al. Architectural Support for Fair Reader-Writer Locking. International Symposium on Microarchitecture (2010).
Vallejo, E., Harris, T., Cristal, A., Unsal, O. & Valero, M. Hybrid Transactional Memory to accelerate safe lock-based transactions. 3rd ACM SIGPLAN Workshop on Transactional Computing (TRANSACT 2008) (2008). at <>
Vallejo, E. et al. Towards Fair Scalable Locking. Workshop on Exploiting Parallelism with Transactional Memory and other Hardware Assisted Methods (EPHAM 2008) (2008). at <>
Galluzzi, M. et al. Implicit Transactional Memory in Kilo-Instruction Multiprocessor. The Twelfth Asia-Pacific Computer Systems Architecture Conference (ACSAC 2007) 339–353 (Springer, 2007).
Vallejo, E. et al. Chip Multiprocessors with Implicit Transactions. 2006 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-06) 167–170 (Academia Press, 2006).