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Falcón, A., Santana, O. J., Ramirez, A. & Valero, M. Tolerating branch predictor latency on SMT. 5th International Symposium on High Performance Computing (ISHPC-V) 86-98 (2003).
Ramirez, A. et al. Trace Cache Redundancy. X Jornadas de Paralelismo 39-44 (1999).
Ramirez, A., Larriba-Pey, J. L. & Valero, M. Trace Cache Redundancy: Red & Blue Traces. Sixth International Symposium on High-Performance Computer Architecture (HPCA'2000) 325-333 (2000).
Rico, A., Ramirez, A. & Valero, M. Trace Filtering of Multithreaded Applications for CMP Memory Simulation. IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS-2013) 134–135 (2013).