Publications

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S. Tomić, Perfumo, C., Kulkarni, C., Armejach, A., Cristal, A., Unsal, O., Harris, T., and Valero, M., EazyHTM, Eager-Lazy Hardware Transactional Memory, 42nd International Symposium on Microarchitecture (MICRO). New York, United States, 2009.
S. Tomić, Akpinar, E., Cristal, A., Ünsal, O. S., and Valero, M., EcoTM: Conflict-Aware Economical Unbounded Hardware Transactional Memory, International Conference on Computational Science, ICCS 2013. Elsevier, www.sciencedirect.com, 2013.
A. Ramirez, Larriba-Pey, J. L., and Valero, M., The Effect of Code Reordering on Branch Prediction, International Conference on Parallel Architectures and Compilation Techniques (PACT 2000). pp. 189-198, 2000.
V. Marjanovic, Labarta, J., Ayguadé, E., and Valero, M., Effective Communication and Computation Overlap with Hybrid MPI/SMPSs. 15th ACM SIGPLAN Annual Symposium on Principles and Practice of Parallel Programming (PPoPP), 2010.
A. Falcón, Ramirez, A., and Valero, M., Effective Instruction Prefetching via Fetch Prestaging, IPDPS05. IEEE-ACM 19th International Parallel and Distributed Processing Symposium. 2005.
B. Maric, Abella, J., and Valero, M., Efficient Cache Architectures for Reliable Hybrid Voltage Operation Using EDC Codes, Proceedings of the Conference on Design, Automation and Test in Europe. EDA Consortium, San Jose, CA, USA, pp. 917–920, 2013.
M. Paolieri, Quiñones, E., Cazorla, F., and Valero, M., Efficient Execution of Mixed Application Workloads in a Hard Real-Time. In Workshop on Reconciling Performance with Predictability (RePP) Oct. 15, 2009, during the ESWEEK, Grenoble, France, 2009.
J. J. Alastruey, Monreal, T., Viñals, V., and Valero, M., Efficient Register File Management in High-ILP Processors. ACACES 2005, Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems, 2005.
T. Ramírez, Santana, O. J., Pajuelo, A., and Valero, M., Efficient runahead threads. PACT 2010. International Conference on Parallel Architectures and Compiler Techniques, 2011.
T. Ramírez, Cristal, A., Pajuelo, A., Santana, O. J., and Valero, M., Eficacia vs. Eficiencia: Una decisión de diseño en Runahead, XVI Jornadas de Paralelismo. Thomson, Granada, Spain, 2005.
E. Lara, Cristal, A., and Valero, M., El Procesador Kilo-Ruanahead, una Alternativa para Reducir el Número de Registros Físicos del Procesador Kilo-Instruction, II Congreso Español de Informática (CEDI 2007). Zaragoza, Spain, 2007.
I. Tanasic, Gelado, I., Cabezas, J., Ramirez, A., Navarro, N., and Valero, M., Enabling Preemptive Multiprogramming on GPUs, 41st International Symposium on Computer Architecture (ISCA). Minneapolis, MN, United States, 2014.
F. Cazorla, Knijnenburg, P., Sakellariou, R., Fernandez, E., Ramirez, A., and Valero, M., Enabling SMT for Real-Time Embedded Systems., European Signal Processing Conference (EUSIPCO). 2004.
O. J. Santana, Ramirez, A., and Valero, M., Enlarging Instruction Streams, IEEE Transactions on Computers, vol. 56, no. 10. pp. 1342-1357, 2007.
A. Cristal, Martínez, J. F., Llosa, J., and Valero, M., Ephemeral Registers with Multicheckpointing. Computer Architecture Department, Universitat Politècnica de Catalunya (UPC), 2003.
F. Cazorla, Medina, P., Fernández, E., Ramirez, A., and Valero, M., Estudio y evaluación de mecanismos de control de la Especulación, In XIII Jornadas de Paralelismo, Lleida (Spain). 2002.
M. Galluzzi, Puente, V., Cristal, A., Beivide, R., Monasterio, J. A. G., and Valero, M., Evaluating Kilo-instruction Multiprocessors, 3rd Workshop on Memory Performance Issues (WMPI-2004). ACM Press, München, Germany, pp. 72–79, 2004.
A. Morari, Gioiosa, R., Wisniewski, R. W., Rosenburg, B., Inglett, T., and Valero, M., Evaluating the impact of tlb misses on future HPC systems, The 26th IEEE International Parallel and Distributed Processing Symposium (IPDPS 2012). IEEE, Shanghai, China, 2012.
Milan Stanic, Palomar, O., Ivan Ratkovic,, Duric, M., Unsal, O., Cristal, A., and Valero, M., Evaluation of vectorization potential of Graph500 on Intels Xeon Phi, International Conference on High Performance Computing {&} Simulation, HPCS 2014. IEEE, Bologna, Italy, pp. 47–54, 2014.
P. A. Castillo, Merelo, J. J., Moreto, M., Cazorla, F., Valero, M., Mora, A. M., Laredo, J. L., and McKee, S. A., Evolutionary system for prediction and optimization of hardware architecture performance. In IEEE Congress on Evolutionary Computation (CEC). Hong Kong, 2008.
M. Duric, Palomar, O., Smith, A., Unsal, O., Cristal, A., Valero, M., and Burger, D., EVX: Vector Execution on Low Power EDGE Cores, ACM/IEEE Design, Automation, and Test in Europe 2014. Dresden, Germany, 2014.
M. Moreto, Cazorla, F., Ramirez, A., and Valero, M., Explaining Dynamic Cache Partitioning Speed Ups, IEEE Computer Architecture Letters, vol. 6, no. 1. pp. 1-12, 2007.
F. Sánchez, Ramirez, A., and Valero, M., Exploiting Different Levels of Parallelism in the Biological Sequence Comparison Problem, 4CCC. 4th Colombian Computing Conference. Bucaramanga (Colombia), 2009.
M. Pericàs, Cristal, A., González, R., Jiménez, D. A., and Valero, M., Exploiting Execution Locality with a Decoupled Kilo-Instruction Processor, 6th International Symposium on High Performance Computing (ISHPC-VI 2005). Springer-Verlag, Nara, Japan, pp. 56–67, 2005.
E. Quiñones, Abella, J., Cazorla, F., and Valero, M., Exploiting Intra-Task Slack Time of Load Operations for DVFS in Hard Real-Time Multi-core Systems, In Work in Progess (WiP), under the the 24nd Euromicro Conference on Real-Time Systems (ECRTS 2011). 2011.
M. Milovanovic, Unsal, O., Cristal, A., Stipić, S., Zyulkyarov, F., and Valero, M., Extending C/C++ Language with Atomic Constructs, II Congreso Español de Informática (CEDI 2007). Zaragoza, Spain, 2007.