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Tomić, S. et al. EazyHTM, Eager-Lazy Hardware Transactional Memory. 42nd International Symposium on Microarchitecture (MICRO) (2009). at <>
Tomić, S., Akpinar, E., Cristal, A., Ünsal, O. S. & Valero, M. EcoTM: Conflict-Aware Economical Unbounded Hardware Transactional Memory. International Conference on Computational Science, ICCS 2013 (2013).
Ramirez, A., Larriba-Pey, J. L. & Valero, M. The Effect of Code Reordering on Branch Prediction. International Conference on Parallel Architectures and Compilation Techniques (PACT 2000) 189-198 (2000).
Marjanovic, V., Labarta, J., Ayguadé, E. & Valero, M. Effective Communication and Computation Overlap with Hybrid MPI/SMPSs. (2010).
Falcón, A., Ramirez, A. & Valero, M. Effective Instruction Prefetching via Fetch Prestaging. IPDPS05. IEEE-ACM 19th International Parallel and Distributed Processing Symposium (2005).
Maric, B., Abella, J. & Valero, M. Efficient Cache Architectures for Reliable Hybrid Voltage Operation Using EDC Codes. Proceedings of the Conference on Design, Automation and Test in Europe 917–920 (2013). at <>
Paolieri, M., Quiñones, E., Cazorla, F. & Valero, M. Efficient Execution of Mixed Application Workloads in a Hard Real-Time. (2009).
Alastruey, J. J., Monreal, T., Viñals, V. & Valero, M. Efficient Register File Management in High-ILP Processors. (2005).
Ramírez, T., Santana, O. J., Pajuelo, A. & Valero, M. Efficient runahead threads. (2011).
Ramírez, T., Cristal, A., Pajuelo, A., Santana, O. J. & Valero, M. Eficacia vs. Eficiencia: Una decisión de diseño en Runahead. XVI Jornadas de Paralelismo (Thomson, 2005). at <>
Lara, E., Cristal, A. & Valero, M. El Procesador Kilo-Ruanahead, una Alternativa para Reducir el Número de Registros Físicos del Procesador Kilo-Instruction. II Congreso Español de Informática (CEDI 2007) (2007).
Cazorla, F. et al. Enabling SMT for Real-Time Embedded Systems. European Signal Processing Conference (EUSIPCO) (2004).
Santana, O. J., Ramirez, A. & Valero, M. Enlarging Instruction Streams. IEEE Transactions on Computers 56, 1342-1357 (2007).
Cristal, A., Martínez, J. F., Llosa, J. & Valero, M. Ephemeral Registers with Multicheckpointing. (2003).
Cazorla, F., Medina, P., Fernández, E., Ramirez, A. & Valero, M. Estudio y evaluación de mecanismos de control de la Especulación. In XIII Jornadas de Paralelismo, Lleida (Spain) (2002).
Galluzzi, M. et al. Evaluating Kilo-instruction Multiprocessors. 3rd Workshop on Memory Performance Issues (WMPI-2004) 72–79 (ACM Press, 2004). at <>
Morari, A. et al. Evaluating the impact of tlb misses on future HPC systems. The 26th IEEE International Parallel and Distributed Processing Symposium (IPDPS 2012) (2012).
Castillo, P. A. et al. Evolutionary system for prediction and optimization of hardware architecture performance. (2008).
Moreto, M., Cazorla, F., Ramirez, A. & Valero, M. Explaining Dynamic Cache Partitioning Speed Ups. IEEE Computer Architecture Letters 6, 1-12 (2007).
Sánchez, F., Ramirez, A. & Valero, M. Exploiting Different Levels of Parallelism in the Biological Sequence Comparison Problem. 4CCC. 4th Colombian Computing Conference (2009).
Pericàs, M., Cristal, A., González, R., Jiménez, D. A. & Valero, M. Exploiting Execution Locality with a Decoupled Kilo-Instruction Processor. 6th International Symposium on High Performance Computing (ISHPC-VI 2005) 56–67 (Springer-Verlag, 2005). at <>
Quiñones, E., Abella, J., Cazorla, F. & Valero, M. Exploiting Intra-Task Slack Time of Load Operations for DVFS in Hard Real-Time Multi-core Systems. In Work in Progess (WiP), under the the 24nd Euromicro Conference on Real-Time Systems (ECRTS 2011) (2011).
Milovanovic, M. et al. Extending C/C++ Language with Atomic Constructs. II Congreso Español de Informática (CEDI 2007) (2007).