Publications

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2004
Pericàs, M., González, R., Cristal, A., Veidenbaum, A. & Valero, M. An Optimized Front-End Physical Register File with Banking and Writeback Filtering. Workshop on Power-Aware Computer Systems (PACS'04) 4–13 (2004).
Cazorla, F., Fernández, E., Ramirez, A. & Valero, M. Optimizing Long-Latency-Load-Aware Fetch Policies for SMT Processors. International Journal of High Performance Computing and Networking (IJHPCN) 2, (2004).
Cristal, A., Ortega, D., Llosa, J. & Valero, M. Out-of-Order Commit Processors. 10th International Symposium on High Performance Computer Architecture (HPCA-10) 48–59 (IEEE Computer Society Press, 2004).
Ramírez, M. A., Cristal, A., Valero, M., Veidenbaum, A. & Villa, L. A. A partitioned instruction queue to reduce instruction wakeup energy. International Journal of High Performance Computing and Networking 1, 153–161 (2004).
Pericas, M., Ayguadé, E., Zalamea, J., Llosa, J. & Valero, M. Performance and Power Evaluation of Clustered VLIW Processors with Functional Units. (2004).
Cazorla, F. et al. Predictable Performance in SMT Processors. Computing Frontiers (CF'04) (2004).
Falcón, A., Stark, J., Ramirez, A., Lai, K. & Valero, M. Prophet/Critic Hybrid Branch Prediction. 31st Annual International Symposium on Computer Architecture (ISCA-31) 250-262 (2004).
Cazorla, F. et al. QoS for High-Performance SMT Processors in Embedded Systems. IEEE Micro 24, 24-31 (2004).
Santana, O. J., Ramirez, A. & Valero, M. Reducing Fetch Architecture Complexity Using Procedure Inlining. 8th Workshop on Interaction between Compilers and Computer Architectures (INTERACT) (2004).
Zalamea, J., Llosa, J., Ayguadé, E. & Valero, M. Register-constrained Modulo Scheduling. (2004).
Álvarez, M., Sánchez, F., Salami, E., Ramirez, A. & Valero, M. Scalability and Complexity of 2-Dimensional SIMD Extensions. XV Jornadas de Paralelismo 190-195 (2004).
González, R., Cristal, A., Pericàs, M., Veidenbaum, A. & Valero, M. Scalable Distributed Register File. 5th Workshop on Complexity-Effective Design 5–14 (2004).
Falcón, A., Santana, O. J., Ramirez, A. & Valero, M. Selecting Where to Simulate SPEC2000 Using Streams Analysis. XV Jornadas de Paralelismo 208--213 (2004).
Zalamea, J., Llosa, J., Ayguadé, E. & Valero, M. Software and Hardware Techniques to Optimize Register File Utilization in VLIW. (2004).
Pajuelo, A., González, A. & Valero, M. Speculative Execution for Hiding Memory Latency. (2004).
Santana, O. J., Falcón, A., Ramirez, A. & Valero, M. Stream Predictor Guided Instruction Decoding. XV Jornadas de Paralelismo 184-189 (2004).
Fernández, E. et al. Throughput versus Quality of Service in SMT processors. Euromicro-DSD (Digital System Design) (2004).
Cristal, A., Santana, O. J., Valero, M. & Martínez, J. F. Toward Kilo-instruction Processors. ACM Transactions on Architecture and Code Optimization 1, 368–396 (2004).
Verdú, J., Nemirovsky, M., García, J. & Valero, M. Traffic Aggregation Impact on the Memory Performance of Networking Applications. (2004).
2003
Santana, O. J., Galluzzi, M., Ramirez, A. & Valero, M. An Analysis of Dynamic Instruction Streams. XIV Jornadas de Paralelismo 527-532 (2003).
González, R., Cristal, A., Ortega, D. & Valero, M. Arquitecturas Basadas en el Contenido. XIV Jornadas de Paralelismo 541–546 (2003).
Cristal, A., Martínez, J. F., Llosa, J. & Valero, M. A Case for Resource Conscious Out-of-Order Processor. MEDEA Workshop MEmory performance: DEaling with Applications , systems and architecture (MEDEA 2003) (2003).
Cristal, A., Martínez, J. F., Llosa, J. & Valero, M. A Case for Resource-conscious Out-of-order Processors. Computer Architecture Letters 2, (2003).
Cristal, A., Martínez, J. F., Llosa, J. & Valero, M. A Case for Resource-conscious Out-of-order Processors. (2003).
Acosta, C., Vajapeyam, S., Ramirez, A. & Valero, M. CDE: A Compiler-driven, Dependence-Centric, Eager-executing Architecture for the Billion Transistors Era. Workshop on Complexity-Effective Design (WCED 2003) (2003).
González, R., Cristal, A., Ortega, D. & Valero, M. Content Aware Register File Organisation. (2003).
Acosta, C., Galluzzi, M., Vajapeyam, S., Ramirez, A. & Valero, M. Dealing with Billions of Transistors. XIV Jornadas de Paralelismo 547-552 (2003).
Cristal, A., Martínez, J. F., Llosa, J. & Valero, M. Ephemeral Registers with Multicheckpointing. (2003).
Cazorla, F., Fernández, E., Ramirez, A. & Valero, M. Improving Memory Latency Aware Fetch Policies for SMT Processors. 5th International Symposium on High Performance Computing (ISHPC-V) 70-85 (2003). at <http://personals.ac.upc.edu/fcazorla/articles/fcazorla_ishpc2003.pdf>
Cristal, A., Ortega, D., Llosa, J. & Valero, M. Kilo-instruction Processors. 5th International Symposium on High Performance Computing (ISHPC-V) 10–25 (Springer-Verlag, 2003).
Santana, O. J., Ramirez, A. & Valero, M. Latency Tolerant Branch Predictors. 2003 International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'03) 30-39 (2003).
Ramírez, M. A., Cristal, A., Veidenbaum, A., Villa, L. A. & Valero, M. A Low-Power-Instruction-Queue Wakeup Mechanism. XIV Jornadas de Paralelismo 533–540 (2003).
Cristal, A., Martínez, J. F., Llosa, J. & Valero, M. Optimal Use of Registers in Aggressive Superscalar Processors. XIV Jornadas de Paralelismo 553–558 (2003).
Cristal, A., Martínez, J. F., Ortega, D., Llosa, J. & Valero, M. Out-of-Order Commit Processors. (2003).
Ramírez, M. A., Cristal, A., Veidenbaum, A., Villa, L. A. & Valero, M. A Simple Low-Energy Instruction Wakeup Mechanism. 5th International Symposium on High Performance Computing (ISHPC-V) 99–112 (Springer-Verlag, 2003).
Falcón, A., Santana, O. J., Ramirez, A. & Valero, M. Tolerating branch predictor latency on SMT. 5th International Symposium on High Performance Computing (ISHPC-V) 86-98 (2003).
2002
García, A., Fernández, E., Medina, P., Ramirez, A. & Valero, M. Analisis y caracterización de los bucles. XIII Jornadas de Paralelismo (2002).
Knijnenburg, P., Ramirez, A., Larriba-Pey, J. L. & Valero, M. Branch classification for SMT fetch gating. 6th Workshop on Multithreaded Execution, Architecture and Compilation (MTEAC6) (2002).
Knijnenburg, P., Ramirez, A., Latorre, F., Larriba-Pey, J. L. & Valero, M. Branch Classification to Control Instruction Fetch in Simultaneous Multithreaded Architectures. International Workshop on Innovative Architecture (IWIA 2002) 67-76 (2002).
Vandierendonck, H., Ramirez, A., Bosschere, K. D. & Valero, M. A comparative study of redundancy in trace caches. Intl. Euro-Par Conference 512-516 (2002).
Santana, O. J. et al. A Comprehensive Analysis of Indirect Branch Prediction. 4th International Symposium on High Performance Computing (ISHPC-4) 133-141 (2002).
Cazorla, F., Medina, P., Fernández, E., Ramirez, A. & Valero, M. Estudio y evaluación de mecanismos de control de la Especulación. In XIII Jornadas de Paralelismo, Lleida (Spain) (2002).
Ramirez, A., Santana, O. J., Larriba-Pey, J. L. & Valero, M. Fetching Instruction Streams. 35th Annual International Symposium on Microarchitecture (MICRO-35) 371-382 (2002).
Cristal, A., Valero, M., González, A. & Llosa, J. Large Virtual ROBs by Processor Checkpointing. (2002). at <http://capinfo.e.ac.upc.edu/PDFs/dir11/file000939.pdf>
Cristal, A. & Valero, M. ROBs Virtuales utilizando checkpoints. XIII Jornadas de Paralelismo (Edicions de la Universitat de Lleida, 2002).
Ramirez, A., Larriba-Pey, J. L., Navarro, C., Valero, M. & Torrellas, J. Software Trace Cache for Commercial Applications. International Journal of Parallel Programming 30, 373-395 (2002).
Falcón, A. et al. Studying New Ways for Improving Adaptive History Length Branch Predictors. 4th International Symposium on High Performance Computing (ISHPC-4) 271-279 (2002).
2001
Falcón, A. et al. An Analysis of Dynamic History Length Fitting. XII Jornadas de Paralelismo, Valencia (Spain) (2001).
Ramirez, A., Larriba-Pey, J. L. & Valero, M. Branch Prediction Using Profile Data. 7th International Euro-Par Conference (Euro-Par'2001) 386-393 (2001).
Ramirez, A. et al. Code Layout Optimizations for Transaction Processing Workloads. 28th Annual International Symposium on Computer Architecture (ISCA-28) 155-164 (2001).

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