Publications

Export 396 results:
Author Title Type [ Year(Asc)]
Filters: Author is Mateo Valero  [Clear All Filters]
2004
A. Pajuelo, González, A., and Valero, M., Aggressive Speculative Execution for Hidding Memory Latency. XV Jornadas de Paralelismo, 2004.
M. March, García, J., Cerdá, L., and Valero, M., Analysis of a high performance DRAM/SRAM memory scheme for fast packet buffers. WEPA-1: Workshop on Embedded Parallel Architectures at HPCA-10, 2004.
J. Verdú, García, J., Nemirovsky, M., and Valero, M., Analysis of Traffic Traces for Stateful Applications. NP3 : Third Workshop on Network Processors and Applications at HPCA-10, 2004.
J. Verdú, García, J., Nemirovsky, M., and Valero, M., Analysis of Traffic Traces for Statefull Applications. XV Jornadas de Paralelismo, 2004.
F. Cazorla, Fernández, E., Ramirez, A., and Valero, M., Approaching a Smart Sharing of Resources in SMT Processors, Workshop on Complexity-Effective Design (WCED). 2004.
M. Pericàs, González, R., Cristal, A., Veidenbaum, A., and Valero, M., Banked Front-End Register File. Computer Architecture Department, Universitat Politècnica de Catalunya (UPC), 2004.
A. Cristal, Martínez, J. F., Llosa, J., and Valero, M., A case for resource-conscious out-of-order processors: towards kilo-instruction in-flight processors, ACM SIGARCH Computer Architecture News, vol. 32, pp. 3–10, 2004.
R. González, Cristal, A., Veidenbaum, A., Pericàs, M., and Valero, M., A clustered Processor based on Content-Aware Register File. Computer Architecture Department, Universitat Politècnica de Catalunya (UPC), 2004.
O. J. Santana, Falcón, A., Ramirez, A., and Valero, M., A Complexity-Effective Decoding Architecture Based on Instruction Streams, Workshop on Complexity-Effective Design (WCED). 2004.
A. Cristal, Santana, O. J., and Valero, M., A Comprehensive Description of Kilo-Instruction Processors, in 5o Congreso Nacional de Computación, Mexico City, Mexico, 2004, pp. 144–154.
R. González, Cristal, A., Ortega, D., Veidenbaum, A., and Valero, M., A Content Aware Integer Register File Organization, in International Symposium on Computer Architecture (ISCA 2004), München, Germany, 2004, pp. 314–324.
F. Cazorla, Fernández, E., Ramirez, A., and Valero, M., DCache Warn: An I-Fetch Policy To Increase SMT Efficiency, 18th International Parallel and Distributed Processing Symposium (IPDPS-2004). IEEE Computer Society Press, 2004.
M. A. Ramírez, Cristal, A., Villa, L. A., Veidenbaum, A., and Valero, M., Direct Instruction Wakeup for OOO processors, in Innovative Architecture for Future Generation High-Performance Processors and System, Maui, Hawaii, United States, 2004.
D. Ortega, Valero, M., and Ayguadé, E., Dynamic Memory Instruction Bypassing. IJPP, International Journal on Parallel Processing . Plenun Published Corporation. Special issue on selected papers from ICS-2003, 2004.
F. Cazorla, Ramirez, A., Valero, M., and Fernández, E., Dynamically Controlled Resource Allocation in SMT Processors, 37th Annual International Symposium on Microarchitecture (MICRO-37). pp. 171-182, 2004.
F. Cazorla, Knijnenburg, P., Sakellariou, R., Fernandez, E., Ramirez, A., and Valero, M., Enabling SMT for Real-Time Embedded Systems., European Signal Processing Conference (EUSIPCO). 2004.
M. Galluzzi, Puente, V., Cristal, A., Beivide, R., Monasterio, J. A. G., and Valero, M., Evaluating Kilo-instruction Multiprocessors, in 3rd Workshop on Memory Performance Issues (WMPI-2004), München, Germany, 2004, pp. 72–79.
F. Cazorla, Knijnenburg, P., Sakellariou, R., Fernandez, E., Ramirez, A., and Valero, M., Feasibility of QoS for SMT by Resource Allocation., Lecture Notes in Computer Science (LNCS) , vol. 3149/2004. 2004.
M. Galluzzi, Puente, V., Cristal, A., Beivide, R., Monasterio, J. A. G., and Valero, M., A first glance at Kilo-instruction based multiprocessors, in International Conference on Computing Frontiers 2004 (CF'04), Ischia, Italy, 2004, pp. 212–221.
A. Cristal, Llosa, J., Valero, M., and Ortega, D., Future ILP processors, International Journal of High Performance Computing and Networking, vol. 2, pp. 1–10, 2004.
C. Acosta, Falcón, A., Ramirez, A., and Valero, M., Heterogeneity-Aware Architectures, XV Jornadas de Paralelismo. pp. 202-207, 2004.
M. Pericas, Ayguadé, E., Zalamea, J., Llosa, J., and Valero, M., High Performance and Low Power VLIW for Numerical Applications. IJHPCN. International Journal of High Performance Computing and Networking, 2004.
J. García, March, M., Cerdá, L., Corbal, J., and Valero, M., A Hybrid DRAM/SRAM Design for Fast Packet Buffers. HPRS. IEEE Workshop on High Performance Switching and Routing, 2004.
F. Cazorla, Knijnenburg, P., Sakellariou, R., Fernández, E., Ramirez, A., and Valero, M., Implicit vs. Explicit Resource Allocation in SMT Processors, 2004 Euromicro Symposium on Digital Systems Design (DSD 2004). Rennes, France, pp. 44-51, 2004.
E. Salami and Valero, M., Initial Evaluation of Multimedia Extensions on VLIW Architectures. Lectures Notes on Computer Science. Editor Springer-Verlag, 2004.
M. A. Ramírez, Cristal, A., Villa, L. A., Veidenbaum, A., and Valero, M., INSTRUCTION WAKEUP MECHANISM: Power and Timing Evaluation, in CIC,s Research and Computing Science, 2004.
M. Galluzzi, Puente, V., Santana, O. J., Acosta, C., Cristal, A., Beivide, R., Monasterio, J. A. G., and Valero, M., Introducing Kilo-instruction Multiprocessors, in XV Jornadas de Paralelismo, Almería, Spain, 2004.
T. Monreal, Viñals, V., González, J., González, A., and Valero, M., Late Allocation and Early Release of Physical Registers. IEEE Transactions on Computers, 2004.
A. Falcón, Santana, O. J., Ramirez, A., and Valero, M., A latency conscious SMT branch predictor architecture, International Journal of High Performance Computing and Networking (IJHPCN), vol. 2, no. 1. pp. 11-21, 2004.
J. J. Alastruey, Monreal, T., Viñals, V., and Valero, M., Limits on Early Release of Physical Registers. XV Jornadas de Paralelismo, 2004.
M. Valero, Santana, O. J., Ramirez, A., and Larriba-Pey, J. L., A Low Complexity Fetch Architecture for High Performance Superscalar Processors, ACM Transactions on Architecture and Compiler Optimizations (TACO), vol. 1, no. 2. pp. 220-245, 2004.
O. J. Santana, Ramirez, A., Larriba-Pey, J. L., and Valero, M., A Low-Complexity Fetch Architecture for High-Performance Superscalar Processors, ACM Transactions on Architecture and Code Optimization, vol. 1, no. 2. pp. 220-245, 2004.
A. Falcón, Ramirez, A., and Valero, M., A Low-Complexity, High-Performance Fetch Unit for Simultaneous Multithreading Processors, 10th International Conference on High Performance Computer Architecture (HPCA-10). Madrid (Spain), pp. 244-253, 2004.
A. Cristal, Santana, O. J., and Valero, M., Maintaining Thousands of In-Flight Instructions, in 10th International Euro-Par 2004 Conference, Pisa, Italy, 2004, pp. 9–20.
M. Pericàs, González, R., Cristal, A., Veidenbaum, A., and Valero, M., An Optimized Front-End Physical Register File with Banking and Writeback Filtering, in Workshop on Power-Aware Computer Systems (PACS'04), Portland, OR, United States, 2004, pp. 4–13.
F. Cazorla, Fernández, E., Ramirez, A., and Valero, M., Optimizing Long-Latency-Load-Aware Fetch Policies for SMT Processors, International Journal of High Performance Computing and Networking (IJHPCN), vol. 2, no. 2. 2004.
A. Cristal, Ortega, D., Llosa, J., and Valero, M., Out-of-Order Commit Processors, in 10th International Symposium on High Performance Computer Architecture (HPCA-10), Madrid, Spain, 2004, pp. 48–59.
M. A. Ramírez, Cristal, A., Valero, M., Veidenbaum, A., and Villa, L. A., A partitioned instruction queue to reduce instruction wakeup energy, International Journal of High Performance Computing and Networking, vol. 1, pp. 153–161, 2004.
M. Pericas, Ayguadé, E., Zalamea, J., Llosa, J., and Valero, M., Performance and Power Evaluation of Clustered VLIW Processors with Functional Units. Lecture Notes on Computer Science, 2004.
F. Cazorla, Knijnenburg, P., Sakellariou, R., Fernández, E., Ramirez, A., and Valero, M., Predictable Performance in SMT Processors, Computing Frontiers (CF'04). 2004.
A. Falcón, Stark, J., Ramirez, A., Lai, K., and Valero, M., Prophet/Critic Hybrid Branch Prediction, 31st Annual International Symposium on Computer Architecture (ISCA-31). pp. 250-262, 2004.
F. Cazorla, Ramirez, A., Valero, M., Knijnenburg, P., Sakellariou, R., and Fernández, E., QoS for High-Performance SMT Processors in Embedded Systems, IEEE Micro, vol. 24. pp. 24-31, 2004.
O. J. Santana, Ramirez, A., and Valero, M., Reducing Fetch Architecture Complexity Using Procedure Inlining, 8th Workshop on Interaction between Compilers and Computer Architectures (INTERACT). 2004.
J. Zalamea, Llosa, J., Ayguadé, E., and Valero, M., Register-constrained Modulo Scheduling. IEEE Transactions on Parallel and Distributed Systems, 2004.
M. Álvarez, Sánchez, F., Salami, E., Ramirez, A., and Valero, M., Scalability and Complexity of 2-Dimensional SIMD Extensions, XV Jornadas de Paralelismo. pp. 190-195, 2004.
R. González, Cristal, A., Pericàs, M., Veidenbaum, A., and Valero, M., Scalable Distributed Register File, in 5th Workshop on Complexity-Effective Design, München, Germany, 2004, pp. 5–14.
A. Falcón, Santana, O. J., Ramirez, A., and Valero, M., Selecting Where to Simulate SPEC2000 Using Streams Analysis, XV Jornadas de Paralelismo. p. 208--213, 2004.
J. Zalamea, Llosa, J., Ayguadé, E., and Valero, M., Software and Hardware Techniques to Optimize Register File Utilization in VLIW. International Journal of Parallel Programming, 2004.
A. Pajuelo, González, A., and Valero, M., Speculative Execution for Hiding Memory Latency. MEDEA Workshop: ?MEmory performance:DEaling with Applications, systems and architecture, 2004.
O. J. Santana, Falcón, A., Ramirez, A., and Valero, M., Stream Predictor Guided Instruction Decoding, XV Jornadas de Paralelismo. pp. 184-189, 2004.

Pages